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Picaso Processor

Embedded Graphics Processor

DATASHEET

Document Revision: 2.0

Document Date: 26th July 2017

Picaso Processor Datasheet

www.4dsystems.com.au

Table of Contents

1. Description .............................................................................................................. 4

2. Features................................................................................................................... 4

3. Applications ............................................................................................................. 5

4. Pin Configuration and Summary ............................................................................... 6

5. Pin Description......................................................................................................... 9

5.1. Display Interface .......................................................................................................... 9

5.2. SPI Interface –Memory Card .................................................................................... 10

5.3. Serial Ports –UARTS .................................................................................................. 10

5.4. Audio Interface........................................................................................................... 11

5.5. Touch Screen Interface.............................................................................................. 12

5.6. GPIO –General Purpose IO ....................................................................................... 12

5.7. System Pins................................................................................................................. 13

6. 4DGL –Software Language ..................................................................................... 13

7. In Circuit Serial Programming ................................................................................. 14

8. Picaso Architecture ................................................................................................ 14

8.1. PmmC Firmware......................................................................................................... 15

9. System Registers Memory Map .............................................................................. 16

10. Memory Cards –FAT16......................................................................................... 18

11. Hardware Tools .................................................................................................... 18

11.1. Programming Tools.................................................................................................. 18

11.2. Evaluation Display Modules .................................................................................... 19

12. 4D Labs - Workshop4 IDE...................................................................................... 20

12.1. Designer Environment............................................................................................. 20

12.2. ViSi Environment...................................................................................................... 20

12.3. ViSi Genie Environment........................................................................................... 21

12.4. Serial Environment................................................................................................... 21

13. Reference Design ................................................................................................. 22

14. Package Details .................................................................................................... 23

15. PCB Land Pattern.................................................................................................. 24

Picaso Processor Datasheet

www.4dsystems.com.au

16. Specifications and Ratings .................................................................................... 25

17. Revision History ................................................................................................... 26

18. Legal Notice ......................................................................................................... 27

19. Contact Information ............................................................................................. 27

Picaso Processor Datasheet

www.4dsystems.com.au

1. Description

The Picaso Processor is a custom embedded 4DGL

graphics controller designed to interface with many

popular OLED and LCD display panels. Powerful

graphics, text, image, animation and countless more

features are built right inside the chip. It offers a

simple plug-n-play interface to many 16-bit 80-Series

colour LCD and OLED displays.

Picaso is designed to work with minimal design effort

as all of the data and control signals are provided by

the chip to interface directly to the display. This offers

enormous advantage to the designer in development

time and cost saving and takes away all of the burden

of low level design.

Note: If using Picaso, please refer to Section 8.1 for

information on customising the PmmC. Please

contact Technical Support or Sales before starting.

Picaso belongs to a family of processors powered by a

highly optimised soft core virtual engine, EVE

(Extensible Virtual Engine). EVE is a proprietary, high

performance virtual processor with an extensive byte-

code instruction set optimised to execute compiled

4DGL programs. 4DGL (4D Graphics Language) was

specifically developed from ground up for the EVE

engine core. It is a high level language which is easy to

learn and simple to understand yet powerful enough

to tackle many embedded graphics applications.

All of the display built-in driver libraries implement

and share the same high-level function interface. This

allows your GUI application to be portable to different

display controller types.

2. Features

Low-cost OLED, LCD and TFT display graphics user

interface solution.

Ideal as a standalone embedded graphics

processor or interface to any host controller as a

graphics co-processor.

Connect to any colour display that supports an 80-

Series 16 bit wide CPU interface. All data and

control signals are provided.

Built in high performance virtual processor core

(EVE) with an extensive byte-code instruction set

optimised for 4DGL, the high level 4D Graphics

Language.

Comprehensive set of built in graphics and

multimedia services.

Display full colour images, animations, icons and

video clips.

14KB of Flash memory for user code storage and

14KB of SRAM for user variables.

13 Digital I/O pins.

I2C interface (Master).

D0…D15, RD, WR, RS, CS – Display interface

FAT16 file services.

2 Asynchronous hardware serial ports

SPI interface support for SDHC/SD memory card

for multimedia storage and data logging purposes

(micro-SD with up to 2GB and SDHC memory

cards starting from 4GB and above).

4-Wire Resistive Touch panel interface.

Audio support for wave files and complex sound

generation with a dedicated 16-bit PWM audio

output.

8 x 16 bit timers with 1 millisecond resolution.

Single 3.3 Volt Supply @25mA typical.

Available in a 64 pin TQFP 10mm x 10mm

package.

RoHS compliant.

Picaso Processor Datasheet

www.4dsystems.com.au

3. Applications

General purposes embedded graphics.

Elevator control systems.

Point of sale terminals.

Electronic gauges and metres.

Test and measurement and general purpose

instrumentation.

Industrial control and Robotics.

Automotive system displays.

GPS navigation systems.

Medical Instruments and applications.

Home appliances and Smart Home Automation.

Security and Access control systems.

Gaming equipment.

Aviation systems.

HMI with touch panels.

Picaso Processor Datasheet

www.4dsystems.com.au

4. Pin Configuration and Summary

Picaso Processor Pin Out

SYMBOL

I/O

DESCRIPTION

IO1

I/O

General Purpose IO1 pin. This pin is 5.0V tolerant.

4-Wire Resistive Touch Screen Right signal. Connect this pin to XR or X+

signal of the touch panel.

4-Wire Resistive Touch Screen Up signal. Connect this pin to YU or Y+

signal of the touch panel.

SCK

SPI Serial Clock output. SD memory card use only. Connect this pin to

the SPI Serial Clock (SCK) signal of the memory card.

SDI

SPI Serial Data Input. SD memory card use only. Connect this pin to the

SPI Serial Data Out (SDO) signal of the memory card.

SDO

SPI Serial Data Output. SD memory card use only. Connect this pin to the

SPI Serial Data In (SDI) signal of the memory card.

RESET

Master Reset signal. Connect a 4.7K resistor from this pin to VCC.

SDCS

SD Memory-Card Chip Select. SD memory card use only. Connect this pin

to the Chip Enable (CS) signal of the memory card.

9, 20, 25, 41

GND

Device Ground.

10, 19, 26, 38, 57

VCC

Device Positive Supply.

I = Input, O = Output, P = Power, A = Analogue

Picaso Processor Datasheet

www.4dsystems.com.au

Picaso Processor Pin Out (continued…)

SYMBOL

I/O

DESCRIPTION

I/O

Display Data Bus bit 5.

I/O

Display Data Bus bit 4.

I/O

Display Data Bus bit 3.

I/O

Display Data Bus bit 2.

I/O

Display Data Bus bit1.

I/O

Display Data Bus bit 0.

I/O

Display Data Bus bit 6.

I/O

Display Data Bus bit 7.

I/O

Display Data Bus bit 8.

I/O

Display Data Bus bit 9.

D10

I/O

Display Data Bus bit 10.

D11

I/O

Display Data Bus bit 11.

D12

I/O

Display Data Bus bit 12.

D13

I/O

Display Data Bus bit 13.

D14

I/O

Display Data Bus bit 14.

D15

I/O

Display Data Bus bit 15.

RX1

Asynchronous Serial port COM1 receive pin, RX1. Connect this pin to

external serial device Transmit (Tx) signal. This pin is 5.0V tolerant.

TX1

Asynchronous Serial port COM1 transmit pin, TX1. Connect this pin to

external serial device receive (Rx) signal. This pin is 5.0V tolerant.

TX0

Asynchronous Serial port Transmit pin, TX. Connect this pin to host micro-

controller Serial Receive (Rx) signal. The host receives data from Picaso

via this pin. This pin is 5.0V tolerant.

RX0

Asynchronous Serial port Receive pin, RX. Connect this pin to host micro-

controller Serial Transmit (Tx) signal. The host transmits data to Picaso via

this pin. This pin is 5.0V tolerant.

RES

Display RESET. Picaso initialises the display by strobing this pin LOW.

Connect this pin to the Reset (RES) signal of the display.

SDA

I/O

I2C Data In/Out.

SCL

I2C Clock Output.

CLK1

Device Clock input 1 of a 12MHz crystal.

CLK2

Device Clock input 2 of a 12MHz crystal.

BUS6

I/O

General Purpose Parallel I/O BUS(0..7), bit 6. This pin is 5.0V tolerant.

BUS7

I/O

General Purpose Parallel I/O BUS(0..7), bit 7. This pin is 5.0V tolerant.

IO5/BUS_

I/O

General Purpose IO5 pin. Also used for BUS_WR signal to write and latch

the data to the parallel GPIO BUS(0..7).

AUDENB

Audio Enable. Connect this pin to amplifier control.

LOW: Enable external Audio amplifier.

HIGH: Disable external Audio amplifier.

AUDIO

Pulse Width Modulated (PWM) Audio output. Connect this pin to a 2

stage low pass filter then into an audio amplifier.

4-Wire Resistive Touch Screen Left signal. Connect this pin to XL or X-

signal of the touch panel.

4-Wire resistive touch screen bottom signal. Connect this pin to YD or Y-

signal of the touch panel.

DCENB

DC-DC high voltage enable signal. This maybe the high voltage that drives

the LCD backlight or the OLED panel supply.

High: Enable DC-DC converter.

Low : Disable DC-DC converter.

BUS0

I/O

General Purpose Parallel I/O BUS(0..7), bit 0. This pin is 5.0V tolerant.

I = Input, O = Output, P = Power, A = Analogue

Picaso Processor Datasheet

www.4dsystems.com.au

Picaso Processor Pin Out (continued…)

SYMBOL

I/O

DESCRIPTION

BUS1

I/O

General Purpose Parallel I/O BUS(0..7), bit 1. This pin is 5.0V tolerant.

BUS2

I/O

General Purpose Parallel I/O BUS(0..7), bit 2. This pin is 5.0V tolerant.

BUS3

I/O

General Purpose Parallel I/O BUS(0..7), bit 3. This pin is 5.0V tolerant.

BUS4

I/O

General Purpose Parallel I/O BUS(0..7), bit 4. This pin is 5.0V tolerant.

BUS5

I/O

General Purpose Parallel I/O BUS(0..7), bit 5. This pin is 5.0V tolerant.

REF

Internal voltage regulator filter capacitor. Connect a 4.7uF to 10uF capacitor

from this pin to Ground.

Display Write strobe signal. Picaso asserts this signal LOW when writing data to

the display. Connect this pin to the Write (WR) signal of the display.

Display Read strobe signal. Picaso asserts this signal LOW when reading data

from the display. Connect this pin to the Read (RD) signal of the display.

Display Chip Select. Picaso asserts this signal LOW when accessing the display.

Connect this pin to the Chip Select (CS) signal of the display.

Display Register Select.

LOW: Display index or status register is selected.

HIGH: Display GRAM or register data is selected.

Connect this pin to the Register Select (RS or A0 or C/D or similar naming

convention) signal of the display.

IO4/BUS_RD

I/O

General Purpose IO4 pin. Also used for BUS_RD signal to read and latch the

data in to the parallel GPIO BUS(0..7).

IO3

I/O

General Purpose IO3 pin. This pin is 5.0V tolerant.

IO2

I/O

General Purpose IO2 pin. This pin is 5.0V tolerant.

I = Input, O = Output, P = Power, A = Analogue

Picaso Processor Datasheet

www.4dsystems.com.au

5. Pin Description

The Picaso Processor provides both a hardware and a

software interface. This section describes in detail the

hardware interface pins of the device.

5.1. Display Interface

The Picaso supports LCD and OLED displays with an 80-

Series 16-bit wide CPU data interface. The connectivity

to the display is easy and straight forward. The Picaso

generates all of the necessary timing to drive the

display.

Operation

Read Display Status Register

Write Display Index Register

Read Display GRAM Data

Write Register or GRAM Data

No Operation

Display Operation Table

D0-D15 pins (Display Data Bus):

The Display Data Bus (D0-D15) is a 16-bit bidirectional

port and all display data writes and reads occur over

this bus. Other control signals such as RW, RD CS, and

RS synchronise the data transfer to and from the

display.

CS pin (Display Chip Select):

The access to the display is only possible when the

Display Chip Select (CS) is asserted LOW. Connect this

pin to the Chip Select (CS) signal of the display.

RS pin (Display Register Select):

The RS signal determines whether a register command

or data is sent to the display.

LOW: Display index or status register is selected.

HIGH: Display GRAM or register data is selected.

Connect this pin to the Register Select (RS) signal of

the display. Different displays utilise various naming

conventions such as RS, A0, C/D or similar. Be sure to

check with your display manufacturer for the correct

name and function.

RES pin (Display Reset):

Display RESET. Picaso initialises the display by strobing

this pin LOW. Connect this pin to the Reset (RES) signal

of the display.

DCENB pin (External DC/DC Enable):

DC-DC high voltage enable signal. This maybe the high

voltage that drives the LCD backlight or the OLED

panel supply.

WR pin (Display Write):

This is the display write strobe signal. The Picaso

asserts this signal LOW when writing data to the

display in conjunction with the display data bus (D0-

D15). Connect this pin to the Write (WR) signal of the

display.

Item

Sym

Min

Typ

Max

Write Low Pulse

tWL

Write High Pulse

tWH

Write Bus Cycle Total

tWT

100

Write Data Setup

tDS

Picaso Processor Datasheet

www.4dsystems.com.au

RD pin (Display Read):

This is the display read strobe signal. The Picaso

asserts this signal LOW when reading data from the

display in conjunction with the display data bus (D0-

D15). Connect this pin to the Read (RD) signal of the

display.

Item

Sym

Min

Typ

Max

Read Low Pulse

tRL

150

Read High Pulse

tRH

150

Read Bus Cycle Total

tRT

300

Read Data Hold

tDH

5.2. SPI Interface –Memory Card

The Picaso supports SD, micro-SD and MMC memory

cards via its hardware SPI interface. The memory card

is used for all multimedia file retrieval such as images,

animations and movie clips and the SPI interface is

dedicated for this purpose only. The memory card can

also be used as general purpose storage for data

logging applications (RAW and FAT16 format support).

Support is available for micro-SD with up to 2GB

capacity and for high capacity HC memory cards

starting from 4GB and above.

SDI pin (SPI Serial Data In):

The SPI Serial Data Input (SDI). SD memory card use

only. Connect this pin to the SPI Serial Data Out (SDO)

signal of the memory card.

SDO pin (SPI Serial Data Out):

The SPI Serial Data Output (SDI). SD memory card use

only. Connect this pin to the SPI Serial Data In (SDI)

signal of the memory card.

SCK pin (SPI Serial Clock):

The SPI Serial Clock output (SCK). SD memory card use

only. Connect this pin to the SPI Serial Clock (SCK)

signal of the memory card.

SDCS pin (SD Memory Card Chip Select):

SD Memory-Card Chip Select (SDCS). SD memory card

use only. Connect this pin to the Chip Enable (CS)

signal of the memory card.

5.3. Serial Ports –UARTS

The Picaso Processor has two dedicated hardware

Asynchronous Serial ports that can communicate with

external serial devices. These are referred to as the

COM0 and the COM1 serial ports.

The primary features are:

Full-Duplex 8 bit data transmission and reception.

Data format: 8 bits, No Parity, 1 Stop bit.

Independent Baud rates from 300 baud up to

256K baud.

Single byte transmits and receives or a fully

buffered service. The buffered service feature

runs in the background capturing and buffering

serial data without the user application having to

constantly poll any of the serial ports. This frees

up the application to service other tasks.

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