ARM DSTREAM-ST Manuale utente
ARM® DSTREAM-ST
Version 1.0
System and Interface Design Reference Guide
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
ARM 100893_0100_00_en
ARM® DSTREAM-ST
System and Interface Design Reference Guide
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
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Document History
Issue Date Confidentiality Change
0100-00 31 March 2017 Non-Confidential First release
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Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in
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Unrestricted Access is an ARM internal classification.
ARM® DSTREAM-ST
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Product Status
The information in this document is Final, that is for a developed product.
Web Address
http://www.arm.com
Conformance Notices
This section contains conformance notices.
Federal Communications Commission Notice
This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).
Class A
Important: This is a Class A device. In residential areas, this device may cause radio interference. The user should take the
necessary precautions, if appropriate.
CE Declaration of Conformity
The system should be powered down when not in use.
It is recommended that ESD precautions be taken when handling DSTREAM-ST equipment.
The DSTREAM-ST modules generate, use, and can radiate radio frequency energy and may cause harmful interference to radio
communications. There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful
interference to radio reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct
the interference by one or more of the following measures:
• Ensure attached cables do not lie across the target board.
• Increase the distance between the equipment and the receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult ARM Support for help.
Note
It is recommended that wherever possible shielded interface cables be used.
ARM® DSTREAM-ST
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Contents
ARM® DSTREAM-ST System and Interface Design
Reference Guide
Preface
About this book ..................................................... ..................................................... 10
Chapter 1 ARM® DSTREAM-ST system design guidelines
1.1 Reset signals ..................................................... ..................................................... 1-13
1.2 Working with Application-Specific Integrated Circuits (ASIC) or System-on-Chips
(SoC) ........................................................... ........................................................... 1-15
1.3 Physical and electrical connection guidelines ............................ ............................ 1-17
Chapter 2 ARM® DSTREAM-ST target interface connections
2.1 About the ARM® JTAG 20 connector pinouts and interface signals ............ ............ 2-20
2.2 About the CoreSight™ 20 connector pinouts and interface signals .......................... 2-22
2.3 About Serial Wire Debug (SWD) ...................................... ...................................... 2-25
2.4 About trace signals .................................................................................................. 2-27
2.5 About JTAG port timing characteristics ................................. ................................. 2-28
2.6 About JTAG port buffering ........................................... ........................................... 2-30
2.7 I/O diagrams for the DSTREAM-ST connectors ...................................................... 2-34
2.8 Voltage domains of the DSTREAM-ST unit .............................. .............................. 2-36
2.9 Series termination .................................................................................................... 2-37
Chapter 3 ARM® DSTREAM-ST USER Input/Output (IO) connections
3.1 About the USER I/O connector pinouts ................................. ................................. 3-39
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Chapter 4 Target board design for tracing with ARM® DSTREAM-ST
4.1 Overview of high-speed design ....................................... ....................................... 4-42
4.2 PCB track impedance .............................................................................................. 4-43
4.3 Signal requirements ................................................ ................................................ 4-44
4.4 Modeling .................................................................................................................. 4-45
Chapter 5 Reference
5.1 About adaptive clocking to synchronize the JTAG port ..................... ..................... 5-47
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List of Figures
ARM® DSTREAM-ST System and Interface Design
Reference Guide
Figure 1-1 Example reset circuit logic ..................................................................................................... 1-14
Figure 1-2 TAP Controllers serially chained within an ASIC ................................................................... 1-15
Figure 1-3 Typical JTAG connection scheme .......................................................................................... 1-17
Figure 1-4 Target interface logic levels ................................................................................................... 1-18
Figure 2-1 ARM JTAG 20 connector pinout ............................................................................................ 2-20
Figure 2-2 CoreSight 20 connector pinout .............................................................................................. 2-22
Figure 2-3 Typical SWD connections ...................................................................................................... 2-25
Figure 2-4 SWD timing diagrams ............................................................................................................ 2-26
Figure 2-5 Clock waveforms ................................................................................................................... 2-27
Figure 2-6 JTAG port timing diagram ...................................................................................................... 2-28
Figure 2-7 JTAG connection without buffers ........................................................................................... 2-30
Figure 2-8 JTAG connection with TDO buffer ......................................................................................... 2-30
Figure 2-9 Daisy-chained JTAG connection without buffers ................................................................... 2-31
Figure 2-10 Daisy-chained JTAG connection with TCK buffers ................................................................ 2-32
Figure 2-11 JTAG connection with de-skewed buffers .............................................................................. 2-33
Figure 2-12 Input ....................................................................................................................................... 2-34
Figure 2-13 Output .................................................................................................................................... 2-34
Figure 2-14 Input/Output ........................................................................................................................... 2-34
Figure 2-15 Reset output .......................................................................................................................... 2-34
Figure 2-16 Reset output with feedback ................................................................................................... 2-34
Figure 2-17 VTRef input ............................................................................................................................ 2-35
Figure 2-18 VTRef input (decoupled) ........................................................................................................ 2-35
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Figure 2-19 AC Ground ............................................................................................................................. 2-35
Figure 3-1 USER I/O connector pinouts ................................................................................................. 3-39
Figure 4-1 Track impedance ................................................................................................................... 4-43
Figure 4-2 Data waveforms ..................................................................................................................... 4-44
Figure 5-1 Basic JTAG port synchronizer ............................................................................................... 5-48
Figure 5-2 Timing diagram for the Basic JTAG synchronizer .................................................................. 5-48
Figure 5-3 JTAG port synchronizer for single rising-edge D-type ASIC design rules ............................. 5-48
Figure 5-4 Timing diagram for the D-type JTAG synchronizer ................................................................ 5-49
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List of Tables
ARM® DSTREAM-ST System and Interface Design
Reference Guide
Table 2-1 ARM JTAG 20 interface pinout table ..................................................................................... 2-20
Table 2-2 ARM JTAG 20 signals ............................................................................................................ 2-20
Table 2-3 CoreSight 20 interface pinout table ....................................................................................... 2-22
Table 2-4 CoreSight 20 signals ............................................................................................................. 2-23
Table 2-5 SWD timing requirements ...................................................................................................... 2-26
Table 2-6 TRACECLK frequencies ........................................................................................................ 2-27
Table 2-7 DSTREAM-ST JTAG Characteristics ..................................................................................... 2-29
Table 2-8 Typical series terminating resistor values .............................................................................. 2-37
Table 3-1 USER I/O pin connections ..................................................................................................... 3-39
Table 4-1 Data setup and hold .............................................................................................................. 4-44
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About this book
DSTREAM-ST System and Interface Design Reference Guide describes the interfaces of the
DSTREAM-ST debug and trace unit, with details about designing ARM® architecture-based ASICs and
PCBs. This document is written for those using DSTREAM-ST or those designing PCBs.
Using this book
This book is organized into the following chapters:
Chapter 1 ARM® DSTREAM-ST system design guidelines
The ARM® DSTREAM-ST debug and trace unit enables powerful software debug and
optimization on an ARM processor-based hardware target. Use the information in this chapter to
design your own ARM-architecture-based devices and Printed Circuit Boards (PCBs) that can be
debugged using the DSTREAM-ST unit.
Chapter 2 ARM® DSTREAM-ST target interface connections
This chapter describes the target connector pinouts and their interface signals available on the
ARM DSTREAM-ST unit.
Chapter 3 ARM® DSTREAM-ST USER Input/Output (IO) connections
This chapter describes the additional input and output connections provided in the ARM
DSTREAM-ST unit.
Chapter 4 Target board design for tracing with ARM® DSTREAM-ST
This chapter describes some considerations for the design of a target board that can be connected
to the DSTREAM-ST trace feature.
Chapter 5 Reference
Lists other information that might be useful when working with DSTREAM-ST.
Glossary
The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those
terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning
differs from the generally accepted meaning.
See the ARM Glossary for more information.
Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms
in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names,
and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text
instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
Preface
About this book
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Altri manuali per DSTREAM-ST
3
Indice
Altri manuali ARM Accessori per computer
