Atmel ATF16V8B Manuale utente

Features

•Industry-standard Architecture

– Emulates Many 20-pin PALs®

– Low-cost Easy-to-use Software Tools

•High-speed Electrically-erasable Programmable Logic Devices

– 10 ns Maximum Pin-to-pin Delay

•Several Power Saving Options

•CMOS and TTL Compatible Inputs and Outputs

– Input and I/O Pull-up Resistors

•Advanced Flash Technology

– Reprogrammable

– 100% Tested

•High-reliability CMOS Process

– 20 Year Data Retention

– 100 Erase/Write Cycles

– 2,000V ESD Protection

– 200 mA Latchup Immunity

•Commercial, and Industrial Temperature Ranges

•Dual-in-line and Surface Mount Packages in Standard Pinouts

•PCI-compliant

•Green Package Options (Pb/Halide-free/RoHS Compliant) Available

1. Description

The ATF16V8B is a high-performance CMOS (electricallyerasable) programmable

logic device (PLD) that utilizes Atmel’s proven electrically-erasable Flash memory

technology. All speed ranges are specified over the full 5V ±10% range for industrial

temperature ranges, and 5V ±5% for commercial temperature ranges.

Several low-power options allow selection of the best solution for various types of

power-limited applications. Each of these options significantly reduces total system

power and enhances system reliability.

The ATF16V8Bs incorporate a superset of the generic architectures, which allows

direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight out-

puts are each allocated eight product terms. Three different modes of operation,

configured automatically with software, allow highly complex logic functions to be

realized.

Device ICC, Standby ICC, Active

ATF16V8B 50 mA 55 mA

ATF16V8BQ 35 mA 40 mA

ATF16V8BQL 5 mA 20 mA

High-

performance

EE PLD

ATF16V8B

ATF16V8BQ

ATF16V8BQL

0364J–PLD–7/05

ATF16V8B/BQ/BQL

Figure 1-1. Block Diagram

2. Pin Configurations

Table 2-1. Pin Configurations (All Pinouts Top View)

Pin Name Function

CLK Clock

I Logic Inputs

I/O Bi-directional Buffers

OE Output Enable

VCC +5V Supply

Figure 2-1. TSSOP Figure 2-2. DIP/SOIC

Figure 2-3. PLCC

I/CLK

GND

VCC

I/O

I9/OE

I/CLK

GND

VCC

I/O

I9/OE

I/O

GND

I9/OE

I/O

I/CLK

VCC

I/O

0364J–PLD–7/05

ATF16V8B/BQ/BQL

3. Absolute Maximum Ratings*

Temperature Under Bias.................................-55oC to +125oC*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Note: 1. Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns.

Maximum output pin voltage is VCC + 0.75V DC,

which may overshoot to 7.0V for pulses of less

than 20 ns.

Storage Temperature......................................-65oC to +150oC

Voltage on Any Pin with

Respect to Ground .......................................-2.0 V to +7.0 V(1)

Voltage on Input Pins

with Respect to Ground

During Programming...................................-2.0 V to +14.0 V(1)

Programming Voltage with

Respect to Ground .....................................-2.0 V to +14.0 V(1)

4. DC and AC Operating Conditions

Commercial Industrial

Operating Temperature (Ambient) 0oC - 70oC-40

oC - 85oC

VCC Power Supply 5V ± 5% 5V ± 10%

0364J–PLD–7/05

ATF16V8B/BQ/BQL

Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

4.1 DC Characteristics

Symbol Parameter Condition Min Typ Max Units

IIL Input or I/O Low

Leakage Current 0 ≤ VIN ≤ VIL(Max) -35 -100 µA

IIH Input or I/O High

Leakage Current 3.5 ≤ VIN ≤ VCC 10 µA

ICC Power Supply

Current, Standby

VCC = Max,

VIN = Max,

Outputs Open

B-10 Com. 55 85 mA

Ind. 55 95 mA

B-15 Com. 50 75 mA

B-15 Ind. 50 80 mA

BQ-10 Com. 35 55 mA

BQL-15 Com. 5 10 mA

BQL-15 Ind. 5 15 mA

ICC2 Clocked Power

Supply Current

VCC = Max,

Outputs Open,

f = 15 MHz

B-10 Com. 60 90 mA

Ind. 60 100 mA

B-15 Com. 55 85 mA

B-15 Ind. 55 95 mA

BQ-10 Com. 40 55 mA

BQL-15 Com. 20 35 mA

BQL-15 Ind. 20 40 mA

IOS(1) Output Short

Circuit Current VOUT = 0.5 V -130 mA

VIL Input Low Voltage -0.5 0.8 V

VIH Input High Voltage 2.0 VCC+0.75 V

VOL Output High Voltage VIN = VIH or VIL,

VCC = Min

IOL = -24 mA

Com., Ind. 0.5 V

VOH Output High Voltage VIN = VIH or VIL,

VCC = Min IOH = -4.0 mA 2.4 V

0364J–PLD–7/05

ATF16V8B/BQ/BQL

4.2 AC Waveforms(1)

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise

specified.

Note: 1. See ordering information for valid part numbers and speed grades.

4.3 AC Characteristics(1)

Symbol Parameter

-10 -15

UnitsMin Max Min Max

tPD Input or Feedback to

Non-Registered Output 8 outputs switching 310315

tCF Clock to Feedback 6 8 ns

tCO Clock to Output 2 7 2 10 ns

tSInput or Feedback

Setup Time 7.5 12 ns

tHHold Time 0 0 ns

tPClock Period 12 16 ns

tWClock Width 6 8 ns

fMAX

External Feedback 1/(tS + tCO)6845MHz

Internal Feedback 1/(tS + tCF)7450MHz

No Feedback 1/(tP)8362MHz

tEA Input to Output Enable — Product Term 3 10 3 15 ns

tER Input to Output Disable — Product Term 2 10 2 15 ns

tPZX OE pin to Output Enable 2 10 2 15 ns

tPXZ OE pin to Output Disable 1.5 10 1.5 15 ns

0364J–PLD–7/05

ATF16V8B/BQ/BQL

4.4 Input Test Waveforms

4.4.1 Input Test Waveforms and Measurement Levels

tR, tF< 5 ns (10% to 90%)

4.4.2 Output Test Loads (Commercial)

CLincludes Test fixture and Probe capacitance

4.5 Pin Capacitance

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%

tested.

Table 4-1. Pin Capacitance (f = 1 MHz, T = 25°C(1))

Typ Max Units Conditions

CIN 58 pF V

IN = 0V

COUT 68 pF V

OUT = 0V

0364J–PLD–7/05

ATF16V8B/BQ/BQL

4.6 Power-up Reset

The registers in the ATF16V8Bs are designed to reset during power-up. At a point delayed

slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the regis-

tered output state will always be high on power-up.

This feature is critical for state machine initialization. However, due to the asynchronous nature

of reset and the uncertainty of how VCC actually rises in the system, the following conditions are

required:

1. The VCC rise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock pin high, and

3. The clock must remain stable during tPR.

Figure 4-1. Power-up Reset Waveforms

4.7 Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either

a high or a low. This feature will simplify testing since any state can be forced into the registers

to control test sequencing. A JEDEC file with preload is generated when a source file with vec-

tors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically

by most of the approved programmers after the programming.

5. Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF16V8B fuse patterns. Once

programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains

accessible.

The security fuse should be programmed last, as its effect is immediate.

Table 4-2. Power-up Reset Parameters

Parameter Description Typ Max Units

tPR Power-up

Reset Time 600 1,000 ns

VRST Power-up

Reset Voltage 3.8 4.5 V

0364J–PLD–7/05

ATF16V8B/BQ/BQL

6. Electronic Signature Word

There are 64 bits of programmable memory that are always available to the user, even if the

device is secured. These bits can be used for user-specific data.

7. Programming/Erasing

Programming/erasing is performed using standard PLD programmers. See CMOS PLD Pro-

gramming Hardware and Software Support for information on software/programming.

8. Input and I/O Pull-ups

All ATF16V8B family members have internal input and I/O pull-up resistors. Therefore, when-

ever inputs or I/Os are not being driven externally, they will float to VCC. This ensures that all

logic array inputs are at known states. These are relatively weak active pull-ups that can easily

be overdriven by TTL-compatible drivers (see input and I/O diagrams below).

Figure 8-1. Input Diagram

Figure 8-2. I/O Diagram

9. Functional Logic Diagram Description

The Logic Option and Functional Diagrams describe the ATF16V8B architecture. Eight config-

urable macrocells can be configured as a registered output, combinatorial I/O, combinatorial

output, or dedicated input.

The ATF16V8B can be configured in one of three different modes. Each mode makes the

ATF16V8B look like a different device. Most PLD compilers can choose the right mode automat-

ically. The user can also force the selection by supplying the compiler with a mode selection.

The determining factors would be the usage of register versus combinatorial outputs and dedi-

cated outputs versus outputs with output enable control.

The ATF16V8B universal architecture can be programmed to emulate many 20-pin PAL

devices. These architectural subsets can be found in each of the configuration modes described

0364J–PLD–7/05

ATF16V8B/BQ/BQL

in the following pages. The user can download the listed subset device JEDEC programming file

to the PLD programmer, and the ATF16V8B can be configured to act like the chosen device.

Check with your programmer manufacturer for this capability.

Unused product terms are automatically disabled by the compiler to decrease power consump-

tion. A security fuse, when programmed, protects the content of the ATF16V8B. Eight bytes (64

fuses) of User Signature are accessible to the user for purposes such as storing project name,

part number, revision, or date. The User Signature is accessible regardless of the state of the

security fuse.

10. Software Support

Atmel-WinCUPL is a free tool, available on Atmel’s web site and can be used to design in all

members of the Atmel ATF16V8B family of SPLDs. Table 10-1 lists popular compilers with the

appropriate device mnemonics

Note: 1. Only applicable for version 3.4 or lower.

11. Macrocell Configuration

Software compilers support the three different OMC modes as different device types. Most com-

pilers have the ability to automatically select the device type, generally based on the register

usage and output enable (OE) usage. Register usage on the device forces the software to

choose the registered mode. All combinatorial outputs with OE controlled by the product term

will force the software to choose the complex mode. The software will choose the simple mode

only when all outputs are dedicated combinatorial without OE control. The different device types

can be used to override the automatic device selection by the software. For further details, refer

to the compiler software manuals.

When using compiler software to configure the device, the user must pay special attention to the

following restrictions in each mode.

In registered mode pin 1 and pin 11 are permanently configured as clock and output enable,

respectively. These pins cannot be configured as dedicated inputs in the registered mode.

In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin

19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have

the feedback option in this mode.

In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing

so, the two inner most pins (pins 15 and 16) will not have the feedback option as these pins are

always configured as dedicated combinatorial output.

Table 10-1. Compiler Mode Selection

Registered Complex Simple Auto Select

ABEL, Atmel-ABEL P16V8R P16V8C P16V8AS P16V8

CUPL, Atmel-WinCUPL G16V8MS G16V8MA G16V8AS G16V8

LOG/iC GAL16V8_R(1) GAL16V8_C7(1) GAL16V8_C8(1) GAL16V8

OrCAD-PLD “Registered” “Complex” “Simple” GAL16V8A

PLDesigner P16V8R P16V8C P16V8C P16V8A

Tango-PLD G16V8R G16V8C G16V8AS G16V8

0364J–PLD–7/05

ATF16V8B/BQ/BQL

11.1 ATF16V8B Registered Mode

PAL Device Emulation/PAL Replacement. The registered mode is used if one or more regis-

ters are required. Each macrocell can be configured as either a registered or combinatorial

output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin,

and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term.

For a combinatorial output or I/O, the output enable is controlled by a product term, and seven

product terms are allocated to the sum term. When the macrocell is configured as an input, the

output enable is permanently disabled.

Any register usage will make the compiler select this mode. The following registered devices

can be emulated using this mode:

16R8 16RP8

16R6 16RP6

16R4 16RP4

Figure 11-1. Registered Configuration for Registered Mode(1)(2)

Notes: 1. Pin 1 controls common CLK for the registered outputs. Pin 11 controls common OE for the reg-

istered outputs. Pin 1 and Pin 11 are permanently configured as CLK and OE.

2. The development software configures all the architecture control bits and checks for proper pin

usage automatically.

Figure 11-2. Combinatorial Configuration for Registered Mode(1)(2)

Notes: 1. Pin 1 and Pin 11 are permanently configured as CLK and OE.

2. The development software configures all the architecture control bits and checks for proper pin

usage automatically.

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