Atmel AT91 ARM Thumb Istruzioni per l'installazione e il funzionamento
AT91SAM7SE Microcontroller Series Schematic
Check List
1. Introduction
This application note is a schematic review check list for systems embedding Atmel’s
AT91SAM7SE series of ARM®Thumb®-based microcontrollers.
It gives requirements concerning the different pin connections that must be consid-
ered before starting any new board design and describes the minimum hardware
resources required to quickly develop an application with the AT91SAM7SE Series. It
does not consider PCB layout constraints.
It also gives advice regarding low-power design constraints to minimize power
consumption.
This application note is not intended to be exhaustive. Its objective is to cover as
many configurations of use as possible.
The Check List table has a column reserved for reviewing designers to verify the line
item has been checked.
AT91 ARM
Thumb-based
Microcontroller
Application Note
6261E–ATARM–18-Dec-07
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6261E–ATARM–18-Dec-07
Application Note
2. Associated Documentation
Before going further into this application note, it is strongly recommended to check the latest
documents for the AT91SAM7SE Series Microcontrollers on Atmel’s Web site.
Table 2-1 gives the associated documentation needed to support full understanding of this appli-
cation note.
Table 2-1. Associated Documentation
Information Document Title
User Manual
Electrical/Mechanical Characteristics
Ordering Information
Errata
AT91SAM7SE Series Product Datasheet
Internal architecture of processor
ARM/Thumb instruction sets
Embedded in-circuit-emulator
ARM7TDMI®Datasheet
Evaluation Kit User Guide AT91SAM7SE-EK Evaluation Board User Guide
Using SDRAM on AT91SAM7SE Microcontrollers Using SDRAM on AT91SAM7SE Microcontrollers
NAND Flash Support in AT91SAM7SE
Microcontrollers NAND Flash Support in AT91SAM7SE Microcontrollers
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6261E–ATARM–18-Dec-07
Application Note
3. Schematic Check List
3.3V Single Power Supply Strategy (On-chip Voltage Regulator Used)
To reduce power consumption, voltage regulator can be put in standby mode.
3.3V Single Power Supply Schematic Example:(1)
On-chip voltage regulator is used - power supply on VDDIO 3.3V
;Signal Name Recommended Pin Connection Description
VDDIN
3.0V to 3.6V
Decoupling/Filtering capacitors
(100 nF and 4.7 µF)(1)(2)
Powers on-chip voltage regulator and ADC.
Decoupling/Filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
VDDOUT Decoupling/Filtering capacitors
(100 nF and 2.2 µF)(1)(2)
Output of the on-chip 1.8V voltage regulator.
Decoupling/Filtering capacitors must be added to
guarantee 1.8V stability
VDDIO
3.0V to 3.6V
or
1.65V to 1.95V
Decoupling capacitor (100 nF)(1)(2)
Powers I/O lines.
Dual voltage range supported.
VDDFLASH 3.0V to 3.6V
Decoupling capacitor (100 nF)(1)(2) Powers Flash (charge pump) and USB transceivers.
3.3V
VDDIN
Voltage
Regulator
VDDOUT
VDDIO
DC/DC Converter
VDDCORE
VDDFLASH
VDDPLL
GND
GND
GND
4.7µF
100nF
100nF
100nF
2.2µF
100nF
100nF
100nF
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6261E–ATARM–18-Dec-07
Application Note
VDDCORE
1.65 to 1.95V
Can be connected directly to VDDOUT pin
Decoupling capacitor (100 nF)(1)(2)
Powers device and flash logic, on-chip RC.
VDDPLL
1.65 to 1.95V
Can be connected directly to VDDOUT pin
Decoupling capacitor (100 nF)(1)(2)
Powers the main oscillator and the PLL.
GND Ground
No separate ground pins are provided for the different
power supplies.
Only GND pins are provided and should be connected as
shortly as possible to the system ground plane.
;Signal Name Recommended Pin Connection Description
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6261E–ATARM–18-Dec-07
Application Note
3.3V and 1.8V Dual Power Supply Strategy (On-chip Voltage Regulator NOT Used and ADC Used)
To reduce power consumption, voltage regulator can be put in standby mode.
3.3V and 1.8V Dual Power Supply Schematic Example:(1)
On-chip voltage regulator is not used - ADC is used - power supply on VDDIO: 3.3V
;Signal Name Recommended Pin Connection Description
VDDIN
3.0V to 3.6V
Decoupling/Filtering capacitors
(100 nF and 4.7 µF)(1)(2)
Powers ADC.
Decoupling/Filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
VDDOUT Decoupling/Filtering capacitors
(100 nF and 2.2 µF)(1)(2)
Output of the on-chip 1.8V voltage regulator.
Decoupling/Filtering capacitors must be added to prevent
on-chip voltage regulator oscillations.
VDDIO
3.0V to 3.6V
or
1.65V to 1.95V
Decoupling capacitor (100 nF)(1)(2)
Powers I/O lines.
Dual voltage range supported.
VDDFLASH 3.0V to 3.6V
Decoupling capacitor (100 nF)(1)(2)
Powers Flash (charge pump) and USB transceivers.
VVDDFLASH must always be superior or equal to
VVDDCORE.
3.3V
VDDIN
VDDOUT
VDDIO
DC/DC Converter
VDDCORE
VDDFLASH
VDDPLL
GND
GND
100nF
100nF
100nF
100nF
1.8V
DC/DC Converter
GND
GND
100nF
GND
100nF
4.7µF
2.2µF
2.2µF
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6261E–ATARM–18-Dec-07
Application Note
VDDCORE
1.65 to 1.95V
Decoupling/Filtering capacitors
(100 nF and 2.2 µF)(1)(2)
Powers device logic, on-chip RC and Flash.
Decoupling/Filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
VDDPLL 1.65 to 1.95V
Decoupling capacitor (100 nF)(1)(2) Powers the main oscillator and the PLL.
GND Ground
No separate ground pins are provided for the different
power supplies.
Only GND pins are provided and should be connected as
shortly as possible to the system ground plane.
;Signal Name Recommended Pin Connection Description
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6261E–ATARM–18-Dec-07
Application Note
3.3V and 1.8V Dual Power Supply Strategy (On-chip Voltage Regulator and ADC NOT Used)
3.3V and 1.8V Dual Power Supply Schematic Example:(1)
On-chip voltage regulator is not used - ADC is not used - power supply on VDDIO: 3.3V
;Signal Name Recommended Pin Connection Description
VDDIN Connected to GND. -
VDDOUT Can be left unconnected. -
VDDIO
3.0V to 3.6V
or
1.65V to 1.95V
Decoupling/Filtering capacitors
(100 nF and 4.7µF)(1)(2)
Powers I/O lines.
Dual voltage range supported.
Decoupling/Filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
VDDFLASH 3.0V to 3.6V
Decoupling capacitor (100 nF)(1)(2)
Powers Flash (charge pump) and USB transceivers.
VVDDFLASH must always be superior or equal to
VVDDCORE.
3.3V
VDDIO
VDDIN
VDDFLASH
DC/DC Converter
VDDCORE
VDDPLL
GND
GND
100nF
1.8V
DC/DC Converter
GND
GND
100nF
GND
100nF
100nF
VDDOUT
NC
4.7µF
2.2µF
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6261E–ATARM–18-Dec-07
Application Note
VDDCORE
1.65 to 1.95V
Decoupling/Filtering capacitors
(100 nF and 2.2 µF)(1)(2)
Powers device logic, on-chip RC and Flash.
Decoupling/Filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
VDDPLL 1.65 to 1.95V
Decoupling capacitor (100 nF)(1)(2) Powers the main oscillator and the PLL.
GND Ground
No separate ground pins are provided for the different
power supplies.
Only GND pins are provided and should be connected as
shortly as possible to the system ground plane.
;Signal Name Recommended Pin Connection Description
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6261E–ATARM–18-Dec-07
Application Note
;Signal Name Recommended Pin Connection Description
Clock, Oscillator and PLL
XIN
XOUT
Main Oscillator
in
Normal Mode
Crystals between 3 and 20 MHz
Capacitors on XIN and XOUT
(crystal load capacitance dependant)
1 kOhm resistor on XOUT only required for
crystals with frequencies lower than 8 MHz.
Internal Equivalent Load Capacitance (CL):
For the AT91SAM7SE512/256: CL = 20 pF
For the AT91SAM7SE32: CL = 11 pF
Crystal Load Capacitance to check (CCRYSTAL).
Example: on the AT91SAM7SE512/256,
for an 18.432 MHz crystal with a load capacitance of
CCRYSTAL = 20 pF, no external capacitors are required
(CCRYSTAL = CL)
Refer to the electrical specifications of the AT91SAM7SE
series datasheet.
XIN
XOUT
Main Oscillator
in
Bypass Mode
XIN: external clock source
XOUT: can be left unconnected.
1.8V Square wave signal (VDDPLL)
External Clock Source up to 50 MHz
Duty Cycle: 40 to 60%
AT91SAM7SE
XIN XOUT GND
CLEXT
CL
CLEXT
CCRYSTAL
1K 8 MHz
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6261E–ATARM–18-Dec-07
Application Note
PLLRC
Second-order filter
Can be left unconnected if PLL not used.
See the Excel spreadsheet:
“ATMEL_PLL_LFT_Filter_CALCULATOR_AT91_xxx.zip”
(available in the software files on the Atmel Web site)
allowing calculation of the best R-C1-C2 component values
for the PLL Loop Back Filter.
R, C1 and C2 must be placed as close as possible to the
pins.
;Signal Name Recommended Pin Connection Description
GND
C1
C2
PLL
PLLRC
R
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