CCS 2820 Manuale utente
OWNER'S
MANUAL
Model
2820
System
Processor
d-
I
California
COlDpater
SystelDs
CCS
MODEL
2820
SYSTEM
PROCESSOR
,USER'S
MANUAL
MANUAL
89000-02820
REV.
A
COPYRIGHT
1981
CALIFORNIA
COMPUTER
SYSTEMS
250
CARIBBEAN
DRIVE
SUNNYVALE
CA
94086
Copyright
1981
by
California
Computer
Systems.
All
rights
reserved.
No
part
of
this
publication
may
be
reproduced
in
any
form
or
by
any
means
without
express
permission
of
California
Computer
Systems.
The
information
contained
in
this
manual
is
believed
to
be
correct
at
the
time
of
publication.
However,
CCS
assumes
no
liability
resulting
from
the
use
of
this
pUblication.
Publication
history:
Revision
A
printed
March
1981
Z-80
is
a
trademark
of
Zilog,
Inc.
CHAPTER
1INTRODUCTION
TABLE OF
CONTENTS
1
.1
B.ASIC FEATURES
............................•..
1-1
1.2
USING
THIS
MANUAL
1-3
1.3
SERVICE
1-3
1.4
SPECIFICATIONS
1-4
CHAPTER
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
CHAPTER
3
2820
CONFIGURATION
THE
CLOCK
JUMPFR
........................•....
THE
WAIT
CONDITION
AND
LENGTH
JUMPERS .
THE
RESET JUMPER .
THE
POWERFAIL JUMPER .
THE
REFRESH
AND
MREQ
JUMPFRS .
THE
S
10
RCLK
JUMPFR .
THE
ADDRESS
SELECT JUt1PERS .
THE
DMA
READY
PIN
.
THE
S
10
INTERFACE
JUr·1PERS
.
THE
INTERRUPT DAISY CHAIN
PADS
.
PROGRAMMING
INFORMATION
2-3
2-3
2-4
2-4
2-4
2-5
2-5
2-6
2-7
2-7
3.1
3.2
3.3
3.4
3.5
THE
CPU
THE
DMA
THE
PIa
THE
CTC
THE
SIO
· .
CONTROLLER
...............•...........
·.
· .
·.
3-1
3-1
3-2
3-3
3-4
THE
Z-80
CPU
................•••..............
Z-80
FAMILY
INTERFACING
..........•...........
THE
PIa
.
THE
810
.
THE
eTC
......••...................•..........
THE
DMA
••••••••••••••••••••••••••••••••••••••
THE
INTERRUPT DAISY
CHAIN
.
Z-80
PERIPHERAL ADDRESSING .
BUS
IMPLEMENTATION
.
THE
SYSTEM
CLOCK
.
CHAPTER
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
2820
HARDWARE
DESIGN
WAIT
CIRCUITRY
4-1
4-1
4-3
4-5
4-5
4-7
4-10
4-11
4-13
4-14
4-14
APPENDIX ATECHNICAL
INFORMATION
A.1
USER-REPLACEABLE
PARTS
A-2
A.2
PARALLEL
CABLE
CONNECTOR
PINOUTS
'.............
A-4
A.3
PARALLEL
ON-BOARD
CONNECTOR
PINOUTS
A-4
A.4
SERIAL
CABLE
CONNECTOR
PINOUTS
A-5
A.5
DEFINITION
OF
RS-232-C
CONFIGURATIONS
A-6
A.6
SIGNAL
CHART
FOR
RS-232-C
CONFIGURATIONS
A-6
A.7
Z-80
CHIP PINOUTS
A-7
A.8
2820
BUS
OUTPUT
WAVEFORMS
A-8
A.9
SCHE~~TIC/LOGIC
DIAGRAM
A-9
APPENDIX BDAISY
CHAIN
CONFIGURATIONS
B.1
THE
INTERRUPT DAISY
CHAIN
B-1
B.2
DAISY-CHAINING
DMA
CONTROLLERS
....•..........
B-1
CHAPTER
1
INTRODUCTION
1.1
BASIC
FEATURES
The
CCS
2820,
the
central
processinq
unit
of
the
CCS-200,
300,
and
400
systems,
has
been
desiqned
to
take
full
advantage
of
high-performance
Z-80
technology.
Besides
the
Z-80
CPU,
the
board
features
four
devices
designed
especially
for
use
with
the
Z-80
CPU: a
Parallel
I/O
Controller
(PIa),
a
Serial
I/O
Controller
(SIO),
a
Clock
Timer
Circuit
(CTC),
and
a
Direct
Memory
Access
Controller
(DMA).
The
relationships
of
these
devices
are
shown
in
Figure
1.1,
a
block
diagram
of
the
2820.
The
Z-80
support
devices
interface
with
each
other
with
a
minimum
of
external
logic.
All
four
peripheral
devices
participate
in
an
interrupt
daisy
chain
to
take
advantage
of
the
powerful
interrupt-processing
capabilities
of
the
Z-80
cpu.
The
PIO
interface
is
configured
for
a
Centronics-type
printer,
while
the
SIO
interface
meets
the
RS-232-C
specifications.
Much
of
the
circuitry
on
the
2820
is'
devoted
to
implementation
of
the
bus
signals,
adapting
the
Z-80
signals
to
the
S-100
bus.
Included
is
a
crystal-controlled
clock
circuit
which
provides
the
2
MHz
bus
signal
and
a 4
MHz
system
clock.
Several
hardware-selectable
options
incorpora~ed
on
the
2820
provide
for
flexibility
in
system
configuration.
All
options
are
hardwired
for
the
standard
confiquration,
eliminating
preliminary
set-up
procedures,
but
users
who
desire
to
select
a
non-standard
option
may
easily
do
so.
User-selectable
options
include
peripheral
base
addresses,
non-maskable
powerfail
interrupts,
and
automatic
wait
state
generation.
I\,)
CO
I\,)
a
(D
r
o
(')
A
o
»
Ci)
:IJ
»
~
PARALLEL
INTERFACE
SERIAL
INTERFACE
LOGIC
I~
I~
5-100
BUS
OMA
ROY
H
Z
1-3
:::0
o
t:1
c:::
(J
1-3
H
o
Z
INTRODUCTION
1.2
USING THIS
MANUAL
1-3
Host
System
200,
300,
and
400
users
will
not
find
it
necessary
to
consult
this
manual;
the
information
they
require
is
in
the
System
Operation
Manual
for
their
particular
system.
This
manual
is
provided
for
those
who
will
at
some
time
reconfigure,
program,
or
trouble-shoot
the
2820.
Chapter
2
provides
instructions
for
all
of
the
configuration
options
of
the
2820.
Full
programming
instructions
for
the
Z-80
family
devices
are
provided
in
the
Programming
Guide
that
is
included
in
the
documentation
package
of
each
system.
However,
device
implementation
often
limits
the
programming
options;
such
limitations
of
the
DHA,
SIO,
PIO,
and
CTC
on
the
2820
are
treated
in
Chapter
3.
Chapter
4
and
the
schematic
and
pinouts
in
Appendix
A
provide
information
necessary
for
trouble-shooting
the
2820.
IEEE
conventions
regarding
signal
names/mnemonics
and
the
identification
of
low-active
signals
by
an
asterisk
after
the
name/mnemonic
(e.g.,
pWR*)
are
followed
throughout
the
manual.
1.3
SERVICE
If
at
some
point
you
need
to
return
your
2820
or
other
CCS
product
to
the
factory
for
service,
first
write
to
the
Customer
Service
Department
at
the
address
given
below
to
obtain
an
~1A
(Return
Materials
Authorization)
number.
Products
returned
without
an
RMA
number
will
be
refused
by
the
Shipping
and
Receiving
Department.
Customer
Service
Department
California
Computer
Systems
253
Caribbean
Drive
Sunnyvale
Ca
94086
1-4
INTRODUCTION
1.4
SPECIFICATIONS
SIZE:
Board:
Connector:
Component
Ht:
POWER
SUPPLY:
+8
Volts
+16
Volts
-16
Volts
Consumption:
10"
long
x
5"
wide
6.365"
long
x
.3"
wide"
2.125"
from
right
of
board
less
than
.5
11
Regulated
On-Board
to
+5
Volts
Regulated
On-Board
to
+12
Volts
Regulated
On-Board
to
-12
Volts
@600
rnA
at
+8
V.
@100
rnA
at
+16
V.
@100
rnA
at
-16
V.
Heat
Burden:
O°C.
to
+70°C.
less
than
90%
116
gram-calories/minute
.48
BTU/minute
ENVIRONMENTAL
REQUIREMENTS:
Temperature:
Humidity:
ON-BOARD
DEVICES:
Z-80
CPU
Z-80
Direct
Memory
Access
Controller
Z-80
Parallel
Input/Output
Controller
Z-80
Serial
Input/Output
Controller
Z-80
Clock/Timer
Circuit
Crystal-Controlled
2and 4
MHz
Clock
Circuitry
INTERFACES:
System Bus:
Peripheral:
ADDITIONAL
FEATURES:
S-100-Based
Jumper-Enabled
MREQ*
and
REFRESH*
lines
Two
RS-232-C
Serial
Interfaces:
DCE
Programmable Baud
Rates
~e-configurabl~
for
DTE
Jumperable
External
Clock,
Port
B
One
Parallel
Printer
Interface
Centronics-Type
Separate
Data
and
Status
Ports
Relectable
Peripheral
Base
Addresses
4
MHz
Operation
Two
Programmable
Real-Time
Clocks
Jumperable
Non-Maskable
Interrupt
on Power
Fail
On-Board
Peripheral
Interrupt
Daisy
Chain
with
Look-Ahead
for
Off-Board
Expansion
DMA
Daisy
Chain
Capability
Jumper-Enabled
Single
or
Double
Wait
State
Gefters,tion
in,J:.iO,MemorYI
andior
HI
Cycles
Low-Power
Schottky
and
MOS
Dev1ces
for
Minimum
Power Consumption
Sockets
for
All
lCs
Fiberglass
Epoxy (FR-4)
PC
Board
Solder-Masked
Both
Sides
Gold-Plated
Connector
Fingers
Silk-Screened
Component
Outlines,
Part
Desi~nations,
Refe~2nce
Numbers
CHAPTER
2
CONFIGURATION
The
2820
includes
a
number
of
user-configurable
options.
None
of
these
options
require
configuration
before
the
board
can
be
installed
and
operated:
all
are
hard-wired
for
standard
operating
parameters
of
Systems
200,
300,
and
400.
However,
jumper
pads
have
been
included
on
the
PC
board
to
allow
selection
of
alternatives
to
some
hard-wired
features.
Selection
of
non-standard
features
involves
the
installation
of
jumper
pins
or
wires
and,
in
most
cases,
the
cutting
of
traces
on
the
PC
board
.
Fiqure
2.1
illustrates
the
Individual
jumpers
and
headers
descriptive
sections
that
follow.
2820
jumper
locations.
are
illustrated
in
the
Indice
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