Cypress Semiconductor CY7C144 Manuale utente

CY7C145, CY7C144

8K x 8/9 Dual-Port Static RAM

with SEM, INT, BUSY

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-06034 Rev. *D Revised December 10, 2008

Features

■True Dual-Ported memory cells that enable simultaneous

reads of the same memory location

■8K x 8 organization (CY7C144)

■8K x 9 organization (CY7C145)

■0.65-micron CMOS for optimum speed and power

■High speed access: 15 ns

■Low operating power: ICC = 160 mA (max.)

■Fully asynchronous operation

■Automatic power down

■TTL compatible

■Master/Slave select pin enables bus width expansion to

16/18 bits or more

■Busy arbitration scheme provided

■Semaphores included to permit software handshaking

between ports

■INT flag for port-to-port communication

■Available in 68-pin PLCC, 64-pin and 80-pin TQFP

■Pb-free packages available

Functional Description

The CY7C144 and CY7C145 are high speed CMOS 8K x 8

and 8K x 9 dual-port static RAMs. Various arbitration schemes

are included on the CY7C144/5 to handle situations when

multiple processors access the same piece of data. Two ports

are provided permitting independent, asynchronous access

for reads and writes to any location in memory. The

CY7C144/5 can be used as a standalone 64/72-Kbit dual-port

static RAM or multiple devices can be combined in order to

function as a 16/18-bit or wider master/slave dual-port static

RAM. An M/S pin is provided for implementing 16/18-bit or

wider memory applications without the need for separate

master and slave devices or additional discrete logic. Appli-

cation areas include interprocessor/multiprocessor designs,

communications status buffering, and dual-port

video/graphics memory.

Each port has independent control pins: chip enable (CE),

read or write enable (R/W), and output enable (OE). Two flags,

BUSY and INT, are provided on each port. BUSY signals that

the port is trying to access the same location currently being

accessed by the other port. The interrupt flag (INT) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from

one port to the other to indicate that a shared resource is in

use. The semaphore logic is comprised of eight shared

latches. Only one side can control the latch (semaphore) at

any time. Control of a semaphore indicates that a shared

resource is in use. An automatic power down feature is

controlled independently on each port by a chip enable (CE)

pin or SEM pin.

Notes

1. BUSY is an output in master mode and an input in slave mode.

2. Interrupt: push-pull output and requires no pull-up resistor.

R/W L

CEL

OEL

A12L

A0L A0R

A12R

R/W R

CER

OE R

CE R

OE R

OEL

R/W LR/W R

I/O7L

I/O

I/ O 7R

I/ O 0R

INT ERRUPT

SEMAPHORE

AR B I T R AT IO N

CONT ROL

I/ O

CONTROL

I/O

MEMORY

ARRAY ADDRESS

DECODER

ADDRESS

DECODER

SE M LSE MR

BUSY

LBU S Y R

INT

LINT

M/S

(7C145) I/O

8L I/ O 8R

(7 C 1 4 5

)

[1 , 2 ]

[2]

[1, 2]

[2]

Logic Block Diagram

CY7C144 CY7C1458K x 8/9 Dual-Port Static RAM

with SEM, INT, BUSY

[+] Feedback

CY7C145, CY7C144

Document #: 38-06034 Rev. *D Page 2 of 21

Pin Configurations

Figure 1. 68-Pin PLCC (Top View)

Figure 2. 64-Pin PLCC (Top View)

3132 3334353637383940414243

5 4 3 2 168 666564636261

A4L

A3L

A2L

A1L

A0L

INTL

BUSYL

GND

M/S

BUSYR

INTR

A0R

I/O2L

I/O3L

I/O4L

I/O5L

GND

I/O6L

I/O7L

VCC

GND

I/O0R

I/O1R

I/O2R

VCC

2728 29 30

98 7 6

A1R

A2R

A3R

A4R

I/O3R

I/O4R

I/O5R

I/O6R

10L

11L

VCC

CEL

SEML

R/WL

OE L

I/O

I/O1L

A8R

A9R

A10R

SEMR

R/W

OER

I/O7R

GND

A11R

A5R

A5L

12L

A12R

CY7C144/5

[3]

[4]

Notes

3. I/O8R on the CY7C145.

4. I/O8L on the CY7C145.

[+] Feedback

CY7C145, CY7C144

Document #: 38-06034 Rev. *D Page 3 of 21

Figure 3. 80-Pin TQFP

Pin Configurations (continued)

/O 2L

/O 3L

/O 4L

/O 5L

/O 6L

/O 7L

VCC

GND

/O0R

/O1R

/O 3R

/O 4R

GND

VCC

OE L

I/O0L

I/O8L

A5L

A12L

A11L

A10L

A9L

A8L

A7L

A6L

CE L

SEM L

R/W L

A4L

A3L

A2L

A1L

A0L

GND

BUSYL

M/S

A0R

A1R

A2R

A3R

A4R

INTL

GND

OER

/O 6R

A12R

A11R

A10R

A9R

A8R

A7R

A6R

CER

SEMR

R/WR

CY7C145

BUSYR

INTR

I/O8R

A5R

I/O7R

I/O1L

Table 1. Pin Definitions

Left Port Right Port Description

I/O0L−7L(8L) I/O0R−7R(8R) Data bus Input/Output

A0L−12L A0R−12R Address Lines

CELCERChip Enable

OELOEROutput Enable

R/WLR/WRRead/Write Enable

SEMLSEMRSemaphore Enable. When asserted LOW, allows access to eight semaphores. The three least signif-

icant bits of the address lines will determine which semaphore to write or read. The I/O0pin is used

when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location.

INTLINTRInterrupt Flag. INTLis set when right port writes location 1FFE and is cleared when left port reads

location 1FFE. INTRis set when left port writes location 1FFF and is cleared when right port reads

location 1FFF.

BUSYLBUSYRBusy Flag

M/S Master or Slave Select

VCC Power

GND Ground

Table 2. Selection Guide

Description 7C144-15

7C145-15

7C144-25

7C145-25

7C144-35

7C145-35

7C144-55

7C145-55 Unit

Maximum Access Time 15 25 35 55 ns

Maximum Operating Current 220 180 160 160 mA

Maximum Standby Current for ISB1 60 40 30 30 mA

[+] Feedback

CY7C145, CY7C144

Document #: 38-06034 Rev. *D Page 4 of 21

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.[5]

Storage Temperature ..................................... −65°C to +150°C

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Supply Voltage to Ground Potential .................−0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State .....................................................−0.5V to +7.0V

DC Input Voltage[6] ..............................................−0.5V to +7.0V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.................................................... >200 mA

Operating Range

Range

Ambient

Temperature VCC

Commercial 0°C to +70°C 5V ±10%

Industrial −40°C to +85°C 5V ±10%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

7C144-15

7C145-15

7C144-25

7C145-25 Unit

Min Max Min Max

VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

VIH Input HIGH Voltage 2.2 2.2 V

VIL Input LOW Voltage 0.8 0.8 V

IIX Input Leakage Current GND < VI< VCC −10 +10 −10 +10 μA

IOZ Output Leakage Current Outputs Disabled, GND < VO< VCC −10 +10 −10 +10 μA

ICC Operating Current VCC = Max., IOUT = 0 mA

Outputs Disabled

Commercial 220 180 mA

Industrial 190

ISB1 Standby Current

(Both Ports TTL Levels)

CELand CER> VIH,

f = fMAX[7] Commercial 60 40 mA

Industrial 50

ISB2 Standby Current

(One Port TTL Level)

CELor CER> VIH,

f = fMAX[7] Commercial 130 110 mA

Industrial 120

ISB3 Standby Current

(Both Ports CMOS Levels)

Both Ports

CE and CER> VCC – 0.2V,

VIN > VCC – 0.2V

or VIN < 0.2V, f = 0[7]

Commercial 15 15 mA

Industrial 30

ISB4 Standby Current

(One Port CMOS Level)

One Port

CELor CER> VCC – 0.2V,

VIN > VCC – 0.2V or

VIN < 0.2V, Active

Port Outputs, f = fMAX[7]

Commercial 125 100 mA

Industrial 115

Notes

5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.

6. Pulse width < 20 ns.

7. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby

ISB3.

[+] Feedback

CY7C145, CY7C144

Document #: 38-06034 Rev. *D Page 5 of 21

Electrical Characteristics Over the Operating Range (continued)

Parameter Description Test Conditions

7C144-35

7C145-35

7C144-55

7C145-55 Unit

Min Max Min Max

VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

VIH Input HIGH Voltage 2.2 2.2 V

VIL Input LOW Voltage 0.8 0.8 V

IIX Input Leakage Current GND < VI< VCC −10 +10 −10 +10 μA

IOZ Output Leakage Current Outputs Disabled, GND < VO< VCC −10 +10 −10 +10 μA

ICC Operating Current VCC = Max., IOUT = 0 mA

Outputs Disabled

Commercial 160 160 mA

Industrial 180 180

ISB1 Standby Current

(Both Ports TTL Levels)

CELand CER> VIH,

f = fMAX[7] Commercial 30 30 mA

Industrial 40 40

ISB2 Standby Current

(One Port TTL Level)

CELor CER> VIH,

f = fMAX[7] Commercial 100 100 mA

Industrial 110 110

ISB3 Standby Current

(Both Ports CMOS Levels)

Both Ports

CE and CER> VCC – 0.2V,

VIN > VCC – 0.2V

or VIN < 0.2V, f = 0[7]

Commercial 15 15 mA

Industrial 30 30

ISB4 Standby Current

(One Port CMOS Level)

One Port

CELor CER> VCC – 0.2V,

VIN > VCC – 0.2V or

VIN < 0.2V, Active

Port Outputs, f = fMAX[7]

Commercial 90 90 mA

Industrial 100 100

Capacitance

Parameter[8] Description Test Conditions Max. Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = 5.0V

10 pF

COUT Output Capacitance 15 pF

Note:

8. Tested initially and after any design or process changes that may affect these parameters.

[+] Feedback

CY7C145, CY7C144

Document #: 38-06034 Rev. *D Page 6 of 21

Figure 4. AC Test Loads and Waveforms

3.0V

GND

90% 90%

10%

≤3ns ≤3ns

10%

ALL INPUT PULSES

(a) Normal Load (Load1)

OUTPUT

C= 30pF

VTH = 1.4V

OUTPUT

C = 30pF

(b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 3)

C= 30pF

OUTPUT

Load (Load 2)

OUTPUT

C= 5pF

R1 = 893Ω

R2 = 347Ω

RTH = 250ΩR1 = 893Ω

R = 347Ω

Switching Characteristics Over the Operating Range[9]

Parameter Description

7C144-15

7C145-15

7C144-25

7C145-25

7C144-35

7C145-35

7C144-55

7C145-55 Unit

Min Max Min Max Min Max Min Max

READ CYCLE

tRC Read Cycle Time 15 25 35 55 ns

tAA Address to Data Valid 15 25 35 55 ns

tOHA Output Hold From Address

Change

3333ns

tACE CE LOW to Data Valid 15 25 35 55 ns

tDOE OE LOW to Data Valid 10 15 20 25 ns

tLZOE[10, 11,12] OE Low to Low Z 3 3 3 3 ns

tHZOE[10, 11,12] OE HIGH to High Z 10 15 20 25 ns

tLZCE[10, 11,12] CE LOW to Low Z 3 3 3 3 ns

tHZCE[10, 11,12] CE HIGH to High Z 10 15 20 25 ns

tPU[12] CE LOW to Power-Up 0 0 0 0 ns

tPD[12] CE HIGH to Power-Down 15 25 35 55 ns

WRITE CYCLE

tWC Write Cycle Time 15 25 35 55 ns

tSCE CE LOW to Write End 12 20 30 45 ns

tAW Address Set-Up to Write End 12 20 30 45 ns

tHA Address Hold From Write End 2 2 2 2 ns

tSA Address Set-Up to Write Start 0 0 0 0 ns

tPWE Write Pulse Width 12 20 25 40 ns

Notes

9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

IOI/IOH and 30-pF load capacitance.

10. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.

11. Test conditions used are Load 3.

12. This parameter is guaranteed but not tested.

[+] Feedback

CY7C145, CY7C144

Document #: 38-06034 Rev. *D Page 7 of 21

tSD Data Set-Up to Write End 10 15 15 25 ns

tHD Data Hold From Write End 0 0 0 0 ns

tHZWE[11,12] R/W LOW to High Z 10 15 20 25 ns

tLZWE[11,12] R/W HIGH to Low Z 3 3 3 3 ns

tWDD[13] Write Pulse to Data Delay 30 50 60 70 ns

tDDD[13] Write Data Valid to Read Data

Valid

25 30 35 40 ns

BUSY TIMING[14]

tBLA BUSY LOW from Address

Match

15 20 20 30 ns

tBHA BUSY HIGH from Address

Mismatch

15 20 20 30 ns

tBLC BUSY LOW from CE LOW 15202030ns

tBHC BUSY HIGH from CE HIGH 15 20 20 30 ns

tPS Port Set-Up for Priority 5 5 5 5 ns

tWB R/W LOW after BUSY LOW 0 0 0 0 ns

tWH R/W HIGH after BUSY HIGH 13 20 30 30 ns

tBDD BUSY HIGH to Data Valid 15 25 35 55 ns

INTERRUPT TIMING[14]

tINS INT Set Time 15 25 25 35 ns

tINR INT Reset Time 15 25 25 35 ns

SEMAPHORE TIMING

tSOP SEM Flag Update Pulse (OE

or SEM)

10 10 15 20 ns

tSWRD SEM Flag Write to Read Time 5 5 5 5 ns

tSPS SEM Flag Contention

Window

5555ns

Notes

13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.

14. Test conditions used are Load 2.

Switching Characteristics Over the Operating Range[9] (continued)

Parameter Description

7C144-15

7C145-15

7C144-25

7C145-25

7C144-35

7C145-35

7C144-55

7C145-55 Unit

Min Max Min Max Min Max Min Max

[+] Feedback

CY7C145, CY7C144

Document #: 38-06034 Rev. *D Page 8 of 21

Switching Waveforms

Figure 5. Read Cycle No. 1 (Either Port Address Access)[15, 16]

Figure 6. Read Cycle No. 2 (Either Port CE/OE Access)[15, 17, 18]

Figure 7. Read Timing with Port-to-Port Delay (M/S=L)[19, 20]

Notes

15. R/W is HIGH for read cycle.

16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.

17. Address valid prior to or coincident with CE transition LOW.

18. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.

19. BUSY = HIGH for the writing port.

20. CEL= CER= LOW.

tRC

tAA

tOHA

DATA VALIDPREVIOUS DATA VALID

DATA OUT

ADDRESS

tACE

tLZOE

tDOE

tHZOE

tHZCE

DATA VALID

DATA OUT

SEM or CE

tLZCE

tPU

ICC

ISB

tPD

VALID

tDDD

tWDD

MATCH

R/WR

DATAINR

DATAOUTL

tWC

ADDRESSR

tPWE

VALID

tSD tHD

ADDRESSL

[+] Feedback

CY7C145, CY7C144

Document #: 38-06034 Rev. *D Page 9 of 21

Figure 8. Write Cycle No. 1: OE Three-State Data I/Os (Either Port)[21, 22, 23]

Figure 9. Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)[21, 23, 24]

Notes

21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal

can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to

be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write

pulse can be as short as the specified tPWE.

23. R/W must be HIGH during all address transitions.

24. Data I/O pins enter high impedance when OE is held LOW during write.

Switching Waveforms (continued)

tAW

tWC

DATA VALID

HIGH IMPEDANCE

tSCE

tSA

tPWE

tHD

tSD

tHA

tHZOE tLZOE

SEM OR CE

R/W

ADDRESS

DATA OUT

DATA IN

tAW

tWC

tSCE

tSA tPWE

tHD

tSD

tHZWE

tHA

HIGH IMPEDANCE

SEM OR CE

R/W

ADDRESS

DATA OUT

DATA IN

tLZWE

DATAVALID

[+] Feedback

CY7C145, CY7C144

Document #: 38-06034 Rev. *D Page 10 of 21

Figure 10. Semaphore Read After Write Timing, Either Side[25]

Figure 11. Semaphore Contention[26, 27, 28]

Notes

25. CE = HIGH for the duration of the above timing (both write and read cycle).

26. I/O0R = I/O0L = LOW (request semaphore); CER= CEL= HIGH

27. Semaphores are reset (available to both ports) at cycle start.

28. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.

Switching Waveforms (continued)

tSOP

tAA

SEM

R/W

I/O0

VALID ADDRESS VALID ADDRESS

tHD

DATA IN VALID DATA OUT VALID

tOHA

A0−A2

tAW

tHA

tACE

tSOP

tSCE

tSD

tSA tPWE

tSWRD tDOE

WRITE CYCLE READ CYCLE

MATCH

tSPS

A0L−A2L

MATCH

R/WL

SEML

A0R−A2R

R/WR

SEMR

[+] Feedback

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