Cypress Semiconductor MoBL CY62148BN Manuale utente

4-Mbit (512K x 8) Static RAM

CY62148BN MoBL®

Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-06517 Rev. *A Revised August 2, 2006

Features

• High Speed

—70ns

• 4.5V–5.5V operation

• Low active power

— Typical active current: 2.5 mA @ f = 1 MHz

— Typical active current:12.5mA @ f = fmax(70 ns)

•Low standby current

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE and OE features

• CMOS for optimum speed/power

• Available in standard lead-free and non-lead-free

32-lead (450-mil) SOIC, 32-lead TSOP II and 32-lead

Reverse TSOP II packages

Functional Description

The CY62148BN is a high-performance CMOS static RAM

organized as 512K words by 8 bits. Easy memory expansion

is provided by an active LOW Chip Enable (CE), an active

LOW OutputEnable (OE), and three-state drivers. This device

has an automatic power-down feature that reduces power

consumption by more than 99% when deselected.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O0through I/O7) is then written into the location

specified on the address pins (A0through A18).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH for read. Under these conditions, the

contents of the memory location specified by the address pins

will appear on the I/O pins.

The eight input/output pins (I/O0through I/O7) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

Logic Block Diagram

A12

A14

A16

COLUMN

DECODER

ROW DECODER

SENSE AMPS

INPUT BUFFER

POWER

DOWN

I/O0

I/O1

I/O2

I/O3

512 xK8

ARRAY

I/O7

I/O6

I/O5

I/O4

A15

A17

A11

A10

[+] Feedback

CY62148BN MoBL®

Document #: 001-06517 Rev. *A Page 2 of 10

Note:

1. Typical values are measured at VCC = 5V, TA= 25°C, and are included for reference only and are not tested or guaranteed.

Pin Configuration

Product Portfolio

Product

VCC Range

Speed Temp.

Power Dissipation

Operating, ICC Standby (ISB2)

f = fmax Typ.[1] Max.Min. Typ. Max. Typ.[1] Max.

CY62148BNLL 4.5 V 5.0V 5.5V 70 ns Com’l 12.5 mA 20 mA 4 µA20 µA

Ind’l

14 19

15 17

I/O

330

232

I/O

Top View

SOIC

TSOP II

GND

I/O

Top View

Reverse

TSOP II

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CY62148BN MoBL®

Document #: 001-06517 Rev. *A Page 3 of 10

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VCC to Relative GND........–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State[2] .....................................–0.5V to VCC +0.5V

DC Input Voltage[2]..................................–0.5V to VCC +0.5V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage...............................................2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Operating Range

Range Ambient

Temperature[3] VCC

Commercial 0°C to +70°C 4.5V–5.5V

Industrial –40°C to +85°C

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

CY62148BN-70

UnitMin. Typ.[1] Max.

VOH Output HIGH Voltage VCC = Min., IOH = – 1 mA 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 V

VIH Input HIGH Voltage 2.2 VCC+0.3 V

VIL Input LOW Voltage –0.3 0.8 V

IIX Input Leakage Current GND ≤VI≤VCC –1 +1 µA

IOZ Output Leakage Current GND ≤VI ≤VCC, Output Disabled –1 +1 µA

ICC VCC Operating

Supply Current f = fMAX = 1/tRC Com’l/Ind’l

IOUT =0 mA

VCC = Max.,

12.5 20 mA

f = 1 MHz 2.5 mA

ISB1 Automatic CE

Power-Down Current

—TTL Inputs

Max. VCC,CE ≤VIH

VIN≤VIHorVIN ≤VIL,

f = fMAX

Com’l/

Ind’l 1.5 mA

ISB2 Automatic CE

Power-Down Current

—CMOSInputs

Max. VCC,

CE ≤VCC – 0.3V,

VIN ≤VCC – 0.3V,

or VIN ≤0.3V, f =0

Com’l/

Ind’l 420 µA

Capacitance[4]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = 5.0V 6pF

COUT Output Capacitance 8pF

AC Test Loads and Waveforms

Notes:

2. VIL (min.) = –2.0V for pulse durations of less than 20 ns.

3. TAis the “Instant On” case temperature

4. Tested initially and after any design or process changes that may affect these parameters.

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE (b)

990Ω

(a)

90%

10%

3.0V

GND

90%

10%

≤ 3 ns ≤3ns

OUTPUT 639Ω

Equivalent to: THEVENIN EQUIVALENT

1.77V

R1 1800Ω

ALL INPUT PULSES

OUTPUT

INCLUDING

JIG AND

SCOPE

990Ω

R1 1800Ω

100 pF

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CY62148BN MoBL®

Document #: 001-06517 Rev. *A Page 4 of 10

Switching Characteristics[5] Over the Operating Range

Parameter Description

62148BNLL-70

UnitMin. Max.

READ CYCLE

tRC Read Cycle Time 70 ns

tAA Address to Data Valid 70 ns

tOHA Data Hold from Address Change 10 ns

tACE CE LOW to Data Valid 70 ns

tDOE OE LOW to Data Valid 35 ns

tLZOE OE LOW to Low Z[6] 5ns

tHZOE OE HIGH to High Z[6, 7] 25 ns

tLZCE CE LOW to Low Z[6] 10 ns

tHZCE CE HIGH to High Z[6, 7] 25 ns

tPU CE LOW to Power-Up 0ns

tPD CE HIGH to Power-Down 70 ns

WRITE CYCLE[8]

tWC Write Cycle Time 70 ns

tSCE CE LOW to Write End 60 ns

tAW Address Set-Up to Write End 60 ns

tHA Address Hold from Write End 0ns

tSA Address Set-Up to Write Start 0ns

tPWE WE Pulse Width 55 ns

tSD Data Set-Up to Write End 30 ns

tHD Data Hold from Write End 0ns

tLZWE WE HIGH to Low Z[6] 5ns

tHZWE WE LOW to High Z[6, 7] 25 ns

Notes:

5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

IOL/IOH and 100-pF load capacitance.

6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of

anyofthesesignalscanterminatethe write.The input dataset-upandholdtimingshouldbereferencedtotheleadingedgeofthesignalthatterminatesthewrite.

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CY62148BN MoBL®

Document #: 001-06517 Rev. *A Page 5 of 10

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min. Typ.[1] Max. Unit

VDR VCC for Data Retention 2.0 V

ICCDR Data Retention Current Com’l LL No input may exceed

VCC + 0.3V

VCC = VDR = 3.0V

CE > VCC – 0.3V

VIN > VCC – 0.3V or

VIN < 0.3V

20 µA

Ind’l LL 20 µA

tCDR[4] Chip Deselect to Data Retention Time 0ns

tR[9] Operation Recovery Time tRC ns

Data Retention Waveform

Switching Waveforms

Read Cycle No.1[10, 11]

Read Cycle No. 2 (OE Controlled)[11, 12]

Notes:

9. Full Device operation requires linear VCC ramp from VDR to VCC(min) >100 ms or stable at Vcc(min) >100 ms.

10.Device is continuously selected. OE, CE = VIL.

11. WE is HIGH for read cycle.

12.Address valid prior to or coincident with CE transition LOW.

3.0V3.0V

tCDR

VDR >2V

DATA RETENTION MODE

VCC

PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE tHZCE

tPD

HIGH

ISB

IMPEDANCE

ADDRESS

DATA OUT

VCC

SUPPLY

CURRENT

[+] Feedback

CY62148BN MoBL®

Document #: 001-06517 Rev. *A Page 6 of 10

Write Cycle No. 1 (CE Controlled)[13]

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]

Notes:

13.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

14.Data I/O is high-impedance if OE = VIH.

15.During this period the I/Os are in the output state and input signals should not be applied.

Switching Waveforms (continued)

tWC

DATA VALID

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

ADDRESS

DATA I/O

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

DATAIN VALID

ADDRESS

DATA I/O

NOTE 15

tHZCE

[+] Feedback

CY62148BN MoBL®

Document #: 001-06517 Rev. *A Page 7 of 10

Write Cycle No.3 (WE Controlled, OE LOW)[13, 14]

Truth Table

CE OE WE I/O0–I/O7Mode Power

H X X High Z Power-Down Standby (ISB)

L L H Data Out Read Active (ICC)

L X L Data In Write Active (ICC)

L H H High Z Selected, Outputs Disabled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

70 CY62148BNLL-70SC 51-85081 32-lead (450-Mil) Molded SOIC Commercial

CY62148BNLL-70SXC 51-85081 32-lead (450-Mil) Molded SOIC (Pb-Free)

CY62148BNLL-70ZC 51-85095 32-lead TSOP II

CY62148BNLL-70ZXC 51-85095 32-lead TSOP II (Pb-Free)

CY62148BNLL-70ZRC 51-85138 32-lead RTSOP II

CY62148BNLL-70SI 51-85081 32-lead (450-Mil) Molded SOIC Industrial

CY62148BNLL-70SXI 51-85081 32-lead (450-Mil) Molded SOIC (Pb-Free)

CY62148BNLL-70ZI 51-85095 32-lead TSOP II

CY62148BNLL-70ZXI 51-85095 32-lead TSOP II (Pb-Free)

CY62148BNLL-70ZRI 51-85138 32-lead RTSOP II

Please contact your local Cypress sales representative for availability of these parts

Switching Waveforms (continued)

DATA VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

ADDRESS

DATAI/O NOTE 15

tHZCE

[+] Feedback

CY62148BN MoBL®

Document #: 001-06517 Rev. *A Page 8 of 10

Package Diagrams

0.546[13.868]

0.440[11.176]

0.101[2.565]

0.050[1.270]

0.014[0.355]

0.118[2.997]

0.004[0.102]

0.047[1.193]

0.006[0.152]

0.023[0.584]

0.793[20.142]

0.450[11.430]

0.566[14.376]

0.111[2.819]

0.817[20.751]

BSC.

0.020[0.508]

MIN.

MAX.

0.012[0.304]

0.039[0.990]

0.063[1.600]

SEATING PLANE

32 LD (450 Mil) SOIC

116

17 32

0.004[0.102]

DIMENSIONS IN INCHES[MM] MIN.

MAX.

PACKAGE WEIGHT 1.42gms

PART #

S32.45 STANDARD PKG.

SZ32.45 LEAD FREE PKG.

51-85081-*B

32-lead (450-Mil) Molded SOIC (51-85081)

32-Lead Thin Small Outline Package Type II (51-85095)

51-85095 **

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CY62148BN MoBL®

Document #: 001-06517 Rev. *A Page 9 of 10

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

More Battery Life is a trademark, and MoBL is a registered trademark, of Cypress Semiconductor. All products and company

names mentioned in this document may be the trademarks of their respective holders.

Package Diagrams (continued)

51-85138-**

32-lead Reverse Thin Small Outline Package Type II (51-85138)

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CY62148BN MoBL®

Document #: 001-06517 Rev. *A Page 10 of 10

Document History Page

Document Title: CY62148BN MoBL®4-Mbit (512K x 8) Static RAM

Document Number: 001-06517

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 426504 See ECN NXR New Data Sheet

*A 485639 See ECN VKN Corrected the typo in the Array size in the Logic Block Diagram

[+] Feedback

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