Cypress Semiconductor Perform STK14D88 Manuale utente

STK14D88

32Kx8 AutoStore™ nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-52037 Rev. ** Revised March 02, 2009

Features

■25, 35, 45 ns Read Access and R/W Cycle Time

■Unlimited Read/Write Endurance

■Automatic Nonvolatile STORE on Power Loss

■Nonvolatile STORE Under Hardware or Software Control

■Automatic RECALL to SRAM on Power Up

■Unlimited RECALL Cycles

■200K STORE Cycles

■20-Year Nonvolatile Data Retention

■Single 3.0V +20%, -10% Power Supply

■Commercial, Industrial Temperatures

■Small Footprint SOIC and SSOP Packages (RoHS-Compliant)

Description

The Cypress STK14D88 is a 256Kb fast static RAM with a

nonvolatile Quantum Trap™ storage element included with each

memory cell.

The SRAM provides fast access and cycle times, ease of use,

and unlimited read and write endurance of a normal SRAM.

Data transfers automatically to the nonvolatile storage cells

when power loss is detected (the STORE operation). On power

up, data is automatically restored to the SRAM (the RECALL

operation). Both STORE and RECALL operations are also

available under software control.

The Cypress nvSRAM is the first monolithic nonvolatile memory

to offer unlimited writes and reads. It is the highest performance,

most reliable nonvolatile memory available.

COLUMN I/O

COLUMN DEC

STATIC RAM

ARRAY

512 x 512

ROW DECODER

INPUT BUFFERS

Quantum Trap

512 x 512

STORE/

RECALL

CONTROL

STORE

RECALL

POWER

CONTROL

SOFTWARE

DETECT

HSB

CCX

CAP

- A

Logic Block Diagram

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STK14D88

Document Number: 001-52037 Rev. ** Page 2 of 17

Pin Configurations Figure 1. Pin Diagram 48-Pin SSOP/32-SOIC

Pin Descriptions

Pin Name I/O Description

A14-A0Input Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array

DQ7-DQ0I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM

EInput Chip Enable: The active low E input selects the device

WInput Write Enable: The active low W enables data on the DQ pins to be written to the address location

latched by the falling edge of E

GInput Output Enable: The active low G input enables the data output buffers during read cycles.

De-asserting G high caused the DQ pins to tri-state.

VCC Power Supply Power: 3.0V, +20%, -10%

HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low

external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this

pin high if not connected. (Connection Optional).

VCAP Power Supply AutoStore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to

nonvolatile storage elements.

VSS Power Supply Ground

NC No Connect Unlabeled pins have no internal connections.

48-Pin SSOP

TOP

VSS

A14

A12

DQ0

DQ1

VCC

DQ2

VCAP

A13

A11

A10

DQ7

DQ6

VSS

NC 23

VCC

HSB

DQ5

DQ3

DQ4

NC NC

32-SOIC

TOP

VSS

A14

A12

DQ0

VCAP

A13

A11

VCC

HSB

DQ1

DQ2

A10

DQ7

DQ5

DQ3

DQ4

DQ6

NCNC

SSOP

Relative PCB Area Usage[1]

Note

1. See “Package Diagrams” on page 15 for detailed package size specifications.

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STK14D88

Document Number: 001-52037 Rev. ** Page 3 of 17

Absolute Maximum Ratings

Voltage on Input Relative to Ground.................–0.5V to 4.1V

Voltage on Input Relative to VSS...........–0.6V to (VCC + 0.5V)

Voltage on DQ0-7 or HSB......................–0.5V to (VCC + 0.5V)

Temperature under Bias ............................... –55°C to 125°C

Storage Temperature.................................... –65°C to 140°C

Power Dissipation.............................................................1W

DC Output Current (1 output at a time, 1s duration).....15mA

NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS

θjc 5.4 C/W; θja 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].

RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS

θjc 6.2 C/W; θja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].

Note: Stresses greater than those listed under “Absolute

Maximum Ratings” maycausepermanent damage tothedevice.

This is a stress rating only, and functional operation of the device

at conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

DC Characteristics

(VCC = 2.7V-3.6V)

Symbol Parameter[2] Commercial Industrial Unit Notes

Min Max Min Max

ICC1Average VCC Current 65

tAVAV = 25ns

tAVAV = 35ns

tAVAV = 45ns

Dependent on output loading and

cycle rate. Values obtained without

output loads.

ICC2Average VCC Current during

STORE 3 3 mA All Inputs Don’t Care, VCC = max

Average current for duration of

STORE cycle (tSTORE)

ICC3Average VCC Current at tAVAV =

200ns

3V, 25°C, Typical

10 10 mA W ≥(VCC– 0.2V)

All Others Cycling, CMOS Levels

Dependent on output loading and

cycle rate. Values obtained without

output loads.

ICC4Average VCAP Current during

AutoStore Cycle 3 3 mA All Inputs Don’t Care

Average current for duration of

STORE cycle (tSTORE)

ISB VCC Standby Current

(Standby, Stable CMOS Input

Levels)

33mAE≥(VCC

– 0.2V)

All Others VIN ≤0.2V or ≥(VCC –

0.2V)

Standby current level after nonvol-

atile cycle complete

IILK Input Leakage Current ±1±1μAV

CC = max

VIN = VSS to VCC

IOLK Off-State Output Leakage Current ±1±1μAV

CC = max

VIN = VSS to VCC, E or G ≥ VIH

VIH Input Logic “1” Voltage 2.0 VCC + .5 2.0 VCC + .5 V All Inputs

VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs

VOH Output Logic “1” Voltage 2.4 2.4 V IOUT =–2mA

Note:

2. The HSB pin has IOUT=-10uA for VOH of 2.4V, this parameter is characterized but not tested

[+] Feedback

STK14D88

Document Number: 001-52037 Rev. ** Page 4 of 17

VOL Output Logic “0” Voltage 0.4 0.4 V IOUT = 4mA

TAOperating Temperature 0 70 -40 85 °C

VCC Operating Voltage 2.7 3.6 2.7 3.6 V 3.3V +20%, -10%

VCAP Storage Capacitance 17 120 17 120 μFBetweenV

CAP pin and VSS, 5V

Rated

DATARData Retention 20 20 K

NVCNonvolatile STORE Operations 200 200 Years @ 55°C

AC Test Conditions

Figure 2. AC Output Loading

Figure 3. AC Output Loading for Tri-state Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ

Capacitance

Parameter[3] Description Test Conditions Max Unit Conditions

CIN Input Capacitance TA= 25°C, f = 1 MHz, 7 pF ΔV = 0 to 3V

COUT Output Capacitance 7 pF ΔV = 0 to 3V

DC Characteristics (continued)

(VCC = 2.7V-3.6V)

Symbol Parameter[2] Commercial Industrial Unit Notes

Min Max Min Max

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times ............................................ <5 ns

Input and Output Timing Reference Levels.................... 1.5V

Output Load..................................See Figure 2 and Figure 3

577

30 pF

789

3.0V

INCLUDING

SCOPE AND

OUTPUT

FIXTURE

577

5 pF

789

3.0V

INCLUDING

SCOPE AND

OUTPUT

FIXTURE

Note

3. These parameters are guaranteed but not tested.

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STK14D88

Document Number: 001-52037 Rev. ** Page 5 of 17

Figure 5. SRAM READ Cycle 2: E Controlled [4, 7]

SRAM READ Cycles #1 and #2

NO. Symbols Parameter STK14D88-25 STK14D88-35 STK14D88-45 Unit

Min Max Min Max Min Max#1 #2 Alt.

ELQV tACS Chip Enable Access Time 25 35 45 ns

AVAV[4] tELEH[4] tRC Read Cycle Time 25 35 45 ns

AVQV[5] tAVQV[5] tAA Address Access Time 25 35 45 ns

GLQV tOE Output Enable to Data Valid 12 15 20 ns

AXQX[5] tAXQX[5] tOH Output Hold after Address Change 3 3 3 ns

ELQX tLZ Address Change or Chip Enable to

Output Active 333ns

EHQZ[6] tHZ Address Change or Chip Disable to

Output Inactive 10 13 15 ns

GLQX tOLZ Output Enable to Output Active 0 0 0 ns

GHQZ[6] tOHZ Output Disable to Output Inactive 10 13 15 ns

10 tELICCH[3] tPA Chip Enable to Power Active 0 0 0 ns

11 tEHICCL[3] tPS Chip Disable to Power Standby 25 35 45 ns

Figure 4. SRAM READ Cycle 1: Address Controlled [4, 5, 6]

Notes

4. W must be high during SRAM READ cycles.

5. Device is continuously selected with E and G both low.

6. Measured ± 200mV from steady state output voltage.

7. HSB must remain high during READ and WRITE cycles.

DATA VALID

tAXQX

tAVQV

DQ (DATA OUT)

ADDRESS

tAVAV

229

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STK14D88

Document Number: 001-52037 Rev. ** Page 6 of 17

SRAM WRITE Cycle #1 and #2

NO. Symbols Parameter STK14D88-25 STK14D88-35 STK14D88-45 Unit

Min Max Min Max Min Max#1 #2 Alt.

12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 ns

13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 ns

14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 ns

15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 ns

16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 ns

17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 ns

18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns

19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 ns

20 tWLQZ[6, 8] tWZ Write Enable to Output Disable 10 13 15 ns

21 tWHQX tOW Output Active after End of Write 3 3 3 ns

Figure 6. SRAM WRITE Cycle 1: W Controlled [8, 9]

Figure 7. SRAM WRITE Cycle 2: E Controlled [8, 9]

DATA OUT

ADDRESS

DATA IN

PREVIOUS DATA

tAVAV

tWHDX

tWHAX

tWLWH

tAVWL

tAVWH

DATA VALID

tWLQZ

tDVWH

HIGH IMPEDANCE

tWHQX

tELWH

tAVAV

tEHDX

tWLEH

tEHAX

tAVEL

tAVEH

DATA VALID

tDVEH

HIGH IMPEDANCE

tELEH

DATA OUT

ADDRESS

DATA IN

Notes

8. If W is low when E goes low, the outputs remain in the high-impedance state.

9. E or W must be ≥VIH during address transitions.

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STK14D88

Document Number: 001-52037 Rev. ** Page 7 of 17

AutoStore/POWER UP RECALL

No. Symbols Alt. Parameter STK14D88 Unit Notes

Min Max

22 tRECALL Power up RECALL Duration 20 ms 10

23 tSTORE tHLHZ STORE Cycle Duration 12.5 ms 11, 12

24 VSWITCH Low Voltage Trigger Level 2.65 V

25 VCCRISE Vcc Rise Time 150 μs

Figure 8. AutoStore /POWER UP RECALL

Note: Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH

23 23

22 22

Notes

10.tHRECALL starts from the time VCC rises above VSWITCH.

11. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.

12.Industrial Grade Devices require 15 ms Max.

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STK14D88

Document Number: 001-52037 Rev. ** Page 8 of 17

Software-Controlled STORE/RECALL Cycle[13, 14]

No. Symbols Parameter STK14D88-25 STK14D88-35 STK14D88-45 Unit Notes

ECont Alternate Min Max Min Max Min Max

26 tAVAV tRC STORE/RECALL Initiation Cycle Time 25 35 45 ns 14

27 tAVEL tAS Address Setup Time 0 0 0 ns

28 tELEH tCW Clock Pulse Width 20 25 30 ns

29 tEHAX Address Hold Time 1 1 1 ns

30 tRECALL RECALL Duration 50 50 50 μs

Figure 9. E and G Controlled Software STORE/RECALL Cycle[14]

DATA VALID HIGH IMPEDANCE

ADDRESS #6ADDRESS #1

DATA VALID

tAVAV

DATA VALID

DQ (DATA

ADDRESS

23 30

tSTORE /tRECALL

tAVAV

tAVEL 28

tELEH

tELAX

Notes

13.The software sequence is clocked on the falling edge of E controlled READs.

14.The six consecutive addressesmust be read in the order listed in the software STORE/RECALL Mode Selection Table. W must behigh during all six consecutive cycles.

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STK14D88

Document Number: 001-52037 Rev. ** Page 9 of 17

Hardware STORE Cycle

NO. Symbols Parameter STK14D88 Unit Notes

Standard Alternate Min Max

31 tDELAY tHLQZ Hardware STORE to SRAM Disabled 1 70 µs 15

32 tHLHX Hardware STORE Pulse Width 15 ns

Figure 10. Hardware STORE Cycle

Soft Sequence Commands

NO. Symbols Parameter STK14D88 Unit Notes

Standard Min Max

33 tSS Soft Sequence Processing Time 70 µs 16, 17

Figure 11. Software Sequence Commands

33 33

Notes

15.Read and Write cycles in progress before HSB is asserted are given this minimum amount of time to complete.

16.This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.

17.Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.

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STK14D88

Document Number: 001-52037 Rev. ** Page 10 of 17

Mode Selection

E W G A14–A0Mode IO Power Notes

H X X X Not Selected Output High Z Standby

L H L X Read SRAM Output Data Active

L L X X Write SRAM Input Data Active

L H L 0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x03F8

Read SRAM

AutoStore Disable

Output Data

Active 18, 19, 20

L H L 0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x07F0

Read SRAM

AutoStore Enable

Output Data

Active 18, 19, 20

L H L 0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

Read SRAM

Output Data

Active

18, 19, 20

0x0FC0 Nonvolatile Store Output High Z ICC2

L H L 0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x0C63

Read SRAM

Nonvolatile Recall

Output Data

Output High Z

Active 18, 19, 20

Notes

18.The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.

19.While there are 15 addresses on the STK14D88, only the lower 14 are used to control software modes

20.I/O state depends on the state of G. The I/O table shown assumes G low.

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