Cypress Semiconductor Rambus XDR CY24271 Manuale utente

CY24272

Rambus®XDR™ Clock Generator with

Zero SDA Hold Time

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-42414 Rev. ** Revised November 9, 2007

Features

■Meets Rambus®Extended Data Rate (XDR™) clocking

requirements

■25 ps typical cycle-to-cycle jitter

❐–135 dBc/Hz typical phase noise at 20 MHz offset

■100 or 133 MHz differential clock input

■300–667 MHz high speed clock support

■Quad (open drain) differential output drivers

■Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4

■Spread Aware™

■2.5V operation

■28-pin TSSOP package

Table 1. Device Comparison

CY24271 CY24272

SDA hold time = 300 ns

(SMBus compliant) SDA hold time = 0 ns

(I2C compliant)

RRC = 200Ωtypical

(Rambus standard drive) RRC = 295Ωminimum

(Reduced output drive)

CLK0

CLK0B

CLK1

CLK1B

CLK2

CLK2B

CLK3

CLK3B

REFCLK,REFCLKB

SCL SDA ID0 ID1

RegA

RegB

RegC

RegD

PLL

Bypass

MUX

/BYPASS EN

Logic Block Diagram

[+] Feedback

CY24272

Document Number: 001-42414 Rev. ** Page 2 of 13

Pinouts

Table 2. Pin Definition - 28 Pin TSSOP

Pin No. Name IO Description

1 VDDP PWR 2.5V power supply for phased lock loop (PLL)

2 VSSP GND Ground

3 ISET I Set clock driver current (external resistor)

4 VSS GND Ground

5 REFCLK I Reference clock input (connect to clock source)

6 REFCLKB I Complement of reference clock (connect to clock source)

7 VDDC PWR 2.5V power supply for core

8 VSSC GND Ground

9 SCL I SMBus clock (connect to SMBus)

10 SDA I SMBus data (connect to SMBus)

11 EN I Output Enable (CMOS signal)

12 ID0 I Device ID (CMOS signal)

13 ID1 I Device ID (CMOS signal)

14 /BYPASS I REFCLK bypassing PLL (CMOS signal)

15 VDD PWR Power supply for outputs

16 CLK3B O Complement clock output

17 CLK3 O Clock output

18 VSS GND Ground

19 CLK2B O Complement clock output

20 CLK2 O Clock output

21 VSS GND Ground

22 VDD PWR Power supply for outputs

23 CLK1B O Complement clock output

24 CLK1 O Clock output

25 VSS GND Ground

26 CLK0B O Complement clock output

27 CLK0 O Clock output

28 VDD PWR Power supply for outputs

Figure 1. Pin Diagram - 28 Pin TSSOP

/BYPASS

REFCLKB

VDD

CLK0B

VSS

CLK2B

CLK3

CLK3B

VDD

VSS

CLK2

CLK0

VSS

CLK1

CLK1B

VDD

VDDP

ISET

VSSC

SDA

ID0

ID1

SCL

VSSP

VSS

REFCLK

VDDC

CY24272

[+] Feedback

CY24272

Document Number: 001-42414 Rev. ** Page 3 of 13

PLL Multiplier

Table 3 shows the frequency multipliers in the PLL, selectable by programming the SMBus registers MULT0, MULT1, and MULT2.

Default multiplier at power up is 4.

Table 3. PLL Multiplier Selection

Input Clock Signal

The XCG receives either a differential (REFCLK/REFCLKB) or a

single-ended reference clocking input (REFCLK).

When the reference input clock is from a different clock source,

it must meet the voltage levels and timing requirements listed in

DC Operating Conditions on page 7 and AC Operating Condi-

tions on page 8.

For a single-ended clock input, an external voltage divider and a

supply voltage, as shown in Figure 2 on page 6, provide a

reference voltage VTH at the REFCLKB pin. This determines the

proper trip point of REFCLK. For the range of VTH specified in

DC Operating Conditions on page 7, the outputs also meet the

DC and AC Operating Conditions tables.

Modes of Operation

The modes of operation are determined by the logic signals

applied to the EN and /BYPASS pins and the values in the five

SMBus Registers: RegTest, RegA, RegB, RegC, and RegD.

Table 5 on page 4 shows selection from one to all four of the

outputs, the Outputs Disabled Mode (EN = low), and Bypass

Mode (EN = high, /BYPASS = low). There is an option reserved

for vendor test. Disabled outputs are set to High Z.

Atpowerup, the SMBusregistersdefault to the lastentryinTable

6on page 5. The value at RegTest is 0. The values at RegA,

RegB, RegC, and RegD are all ‘1’. Thus, all outputs are

controlled by the logic applied to EN and /BYPASS.

Notes

1. Output frequencies shown in Table 3 are based on nominal input frequencies of 100 MHz and 133.3 MHz. The PLL multipliers are applicable to spread spectrum

modulated input clock with maximum and minimum input cycle time. The REFSEL bit in SMBus 81h is set correctly as shown.

2. Default PLL multiplier at power up.

MULT2 MULT1 MULT0 REFCLK = 100 MHz[1], REFSEL = 0 REFCLK=133MHz[1],REFSEL=1

0 0 0 3 300 400

001 4 400

[2] –

0 1 0 5 500 667

0 1 1 6 600 –

1 0 0 Reserved – –

1 0 1 9/2 450 600

1 1 0 Reserved – –

1 1 1 15/4 375 500

Table 4. SMBus Device Addresses for CY24272

XCG Hex

Address 8-bit SMBus Device Address Including Operation

Device Operation Five Most Significant Bits ID1 ID0 WR# / RD

0Write D8

11011

00 0

Read D9 1

1Write DA 01 0

Read DB 1

2Write DC 10 0

Read DD 1

3Write DE 11 0

Read DF 1

[+] Feedback

CY24272

Document Number: 001-42414 Rev. ** Page 4 of 13

Device ID and SMBus Device Address

The device ID (ID0 and ID1) is a part of the SMBus device 8-bit

address. The least significant bit of the address designates a

write or read operation. Table 4 on page 3 shows the addresses

for four CY24272 devices on the same SMBus.

SMBus Protocol

The CY24272 is a slave receiver supporting operations in the

word and byte modes described in sections 5.5.4 and 5.5.5 of

the SMBus Specification 2.0.

DC specifications are modified to Rambus standard to support

1.8, 2.5, and 3.3 volt devices. Time out detection and packet

error protocol SMBus features are not supported.

Hold time for SDA is reduced relative to the CY24271, so that it

is compatible with I2C.

SMBus Data Byte Definitions

Three data bytes are defined for the CY24272. Byte 0 is for

programming the PLL multiplier registers and clock output

registers.

The definition of Byte 2 is shown inTable 6, Table 7, and Table 8

on page 5. The upper five bits are the revision numbers of the

device and the lower three bits are the ID numbers assigned to

the vendor by Rambus.

Notes

3. Bypass Mode: REFCLK bypasses the PLL to the output drivers.

4. Default mode of operation is at power up.

Table 5. Modes of Operation for CY24272

EN /BYPASS RegTest RegA RegB RegC RegD CLK0/CLK0B CLK1/CLK1B CLK2/CLK2B CLK3/CLK3B

L X X X X X X High Z High Z High Z High Z

H X 1 X X X X Reserved for Vendor Test

H L 0 X X X X REFCLK/

REFCLKB[3] REFCLK/

REFCLKB REFCLK/

REFCLKB

H H 0 0 0 0 0 High Z High Z High Z High Z

H H 0 0 0 0 1 High Z High Z High Z CLK/CLKB

H H 0 0 0 1 0 High Z High Z CLK/CLKB High Z

H H 0 0 0 1 1 High Z High Z CLK/CLKB CLK/CLKB

H H 0 0 1 0 0 High Z CLK/CLKB High Z High Z

H H 0 0 1 0 1 High Z CLK/CLKB High Z CLK/CLKB

H H 0 0 1 1 0 High Z CLK/CLKB CLK/CLKB High Z

H H 0 0 1 1 1 High Z CLK/CLKB CLK/CLKB CLK/CLKB

H H 0 1 0 0 0 CLK/CLKB High Z High Z High Z

H H 0 1 0 0 1 CLK/CLKB High Z High Z CLK/CLKB

H H 0 1 0 1 0 CLK/CLKB High Z CLK/CLKB High Z

H H 0 1 0 1 1 CLK/CLKB High Z CLK/CLKB CLK/CLKB

H H 0 1 1 0 0 CLK/CLKB CLK/CLKB High Z High Z

H H 0 1 1 0 1 CLK/CLKB CLK/CLKB High Z CLK/CLKB

H H 0 1 1 1 0 CLK/CLKB CLK/CLKB CLK/CLKB High Z

HH 0

[4] 1[4] 1[4] 1[4] 1[4] CLK/CLKB CLK/CLKB CLK/CLKB CLK/CLKB

[+] Feedback

CY24272

Document Number: 001-42414 Rev. ** Page 5 of 13

Note

5. RW = Read and Write, RO = Read Only, POD = Power on default. See Table 3 on page 3 for PLL multipliers and Table 5 on page 4 for clock output selections.

Table 6. Command Code 80h[5]

Bit Register POD Type Description

7 Reserved 0 RW Reserved (no internal function)

6 MULT2 0 RW PLL Multiplier Select (reference Table 3 on page 3)

5MULT1 0 RW

4MULT0 1 RW

3 RegA 1 RW Clock 0 Output Select

2 RegB 1 RW Clock 1 Output Select

1 RegC 1 RW Clock 2 Output Select

0 RegD 1 RW Clock 3 Output Select

Table 7. Command Code 81h[5]

Bit Register POD Type Description

7 Reserved 0 RW Reserved (no internal function)

6 Reserved 0 RW

5 Reserved 0 RW

4 Reserved 0 RW

3 Reserved 1 RW Reserved (must be set to ‘1’ for proper operation)

2 REFSEL 0 RW Reference Frequency Select (reference Table 3 on page 3)

1 Reserved 0 RW Reserved (must be set to ‘0’ for proper operation)

0 RegTest 0 RW Reserved (must be set to ‘0’ for proper operation)

Table 8. Command Code 82h[5]

Bit Register POD Type Description

7Device

Revision

Number

? RO Contact factory for Device Revision Number information.

6?RO

5?RO

4?RO

3?RO

2 Vendor ID 0 RO Rambus assigned Vendor ID Code

11RO

00RO

[+] Feedback

CY24272

Document Number: 001-42414 Rev. ** Page 6 of 13

Figure 2. Differential and Single-Ended Clock Inputs

Absolute Maximum Conditions

Parameter Description Condition Min Max Unit

VDD Clock Buffer Supply Voltage –0.5 4.6 V

VDDC Core Supply Voltage –0.5 4.6 V

VDDP PLL Supply Voltage –0.5 4.6 V

VIN Input Voltage (SCL and SDA) Relative to VSS –0.5 4.6 V

Input Voltage (REFCLK/REFCLKB)Relative to VSS –0.5 VDD + 1.0 V

Input Voltage Relative to VSS –0.5 VDD + 0.5 V

TSTemperature, Storage Non-functional –65 150 °C

TATemperature, Operating Ambient Functional 0 70 °C

TJTemperature, Junction Functional – 150 °C

ØJA Junction to Ambient thermal resis-

tance Zero air flow – 100 °C/W

ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V

REFCLKB

REFCLK Input

XDR Clock Generator

Input

XDR Clock Generator

REFCLK

Supply Voltage

VTH

Differential Input Single-ended Input

[+] Feedback

CY24272

Document Number: 001-42414 Rev. ** Page 7 of 13

DC Operating Conditions

Parameter Description Condition Min Max Unit

VDDP Supply Voltage for PLL 2.5V ± 5% 2.375 2.625 V

VDDC Supply Voltage for Core 2.5V ± 5% 2.375 2.625 V

VDD Supply Voltage for Clock Buffers 2.5V ± 5% 2.375 2.625 V

VIHCLK Input High Voltage, REFCLK/REFCLKB 0.6 0.95 V

VILCLK Input Low Voltage, REFCLK/REFCLKB –0.15 +0.15 V

VIXCLK[6] Crossing Point Voltage, REFCLK/REFCLKB 200 550 mV

ΔVIXCLK[6] Difference in Crossing Point Voltage, REFCLK/REFCLKB – 150 mV

VIH Input Signal High Voltage at ID0, ID1, EN, and /BYPASS 1.4 2.625 V

VIL Input Signal Low Voltage at ID0, ID1, EN, and /BYPASS –0.15 0.8 V

VIH,SM Input Signal High Voltage at SCL and SDA[7] 1.4 3.465 V

VIL,SM Input Signal Low Voltage at SCL and SDA –0.15 0.8 V

VTH[8] Input Threshold Voltage for single-ended REFCLK 0.35 0.5VDD V

VIH,SE Input Signal High Voltage for single-ended REFCLK VTH + 0.3 2.625 V

VIL,SE Input Signal Low Voltage for single-ended REFCLK –0.15 VTH – 0.3 V

TAAmbient Operating Temperature 0 70 °C

Notes

6. Not 100% tested except VIXCLK and ΔVIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.

7. This range of SCL and SDA input high voltage enables the CY24272 for use with 3.3V, 2.5V, or 1.8V SMBus voltages.

8. Single-ended operation guaranteed only when 0.8 < (VIH,SE – VTH)/(VTH – VIL,SE) < 1.2.

[+] Feedback

CY24272

Document Number: 001-42414 Rev. ** Page 8 of 13

AC Operating Conditions

The AC operating conditions follow.[6]

Parameter Description Condition Min Max Unit

tCYCLE,IN REFCLK, REFCLKB input cycle time REFSEL = 0, /BYPASS = High 9 11 ns

REFSEL = 1, /BYPASS = High 7 8 ns

/BYPASS = Low 4 – ns

tJIT,IN(cc) Input Cycle to Cycle Jitter[9] –185ps

tDCIN[10] Input Duty Cycle Over 10,000 cycles 40% 60% tCYCLE

tRIN / tFIN Rise and Fall Times Measured at 20%–80% of input

voltage for REFCLK and

REFCLKB inputs

175 700 ps

ΔtRIN / tFIN Rise and Fall Times Difference – 150 ps

pMIN[11] Modulation Index for triangular modulation – 0.6 %

Modulation Index for non-triangular modulation – 0.5[12] %

fMIN[11] Input Frequency Modulation 30 33 kHz

tSR,IN Input Slew Rate (measured at 20%–80% of

input voltage) for REFCLK 14V/ns

CIN,REF Capacitance at REFCLK inputs – 7 pF

CIN,CMOS Capacitance at CMOS inputs – 10 pF

fSCL SMBus clock frequency input in SCL pin DC 100 kHz

DC Electrical Specifications

Parameter Description Min Typ Max Unit

VOX[6] Differential output crossing point voltage[13] –1.08–V

VCOS[6] Output voltage swing (peak-to-peak single-ended)[14] –400–mV

VOL,ABS Absolute output low voltage at CLK[3:0], CLK[3:0]B[15] 0.85 – – V

VISET Reference voltage for swing controlled current, IREF 0.98 1.0 1.02 V

IDD[7] Power Supply Current at 2.625V, fref = 100 MHz, and fout = 300 MHz – – 85 mA

IDD[7] Power Supply Current at 2.625V, fref = 133 MHz, and fout = 667 MHz – – 125 mA

IOL/IREF Ratio of output low current to reference current[16] 6.8 7.0 7.2

IOL,ABS Minimum current at VOL,ABS[17] 25 – – mA

VOL,SDA SDAoutputlowvoltageattestconditionofSDAoutputlowcurrent=4mA – – 0.4 V

IOL,SDA SDA output low voltage at test condition of SDA voltage = 0.8V 6 – – mA

IOZ Current during High Z per pin at CLK[3:0], CLK[3:0]B – – 10 μA

ZOUT Output dynamic impedance when clock output signal is at VOL = 0.9V[18] 1000 – – Ω

Notes

9. Jitter measured at crossing points and is the absolute value of the worst case deviation.

10.Measured at crossing points.

11. If input modulation is used; input modulation is allowed but not required.

12.The amount of allowed spreading for any non-triangular modulation is determined bythe induced downstream tracking skew that cannot exceed theskew generated

by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.

13.VOX is measured on external divider network.

14.VCOS = (clock output high voltage – clock output low voltage), measured on the external divider network.

15.VOL_ABS is measured at the clock output pins of the package.

16.IREF is equal to VISET/RRC.

17.Minimum IOL,ABS is measured at the clock output pin with RRC = 266 ohms or less.

18.ZOUT is defined at the output pins as (0.94V – 0.90V)/(I0.94 – I0.90) under conditions specified for IOL, ABS.

[+] Feedback

CY24272

Document Number: 001-42414 Rev. ** Page 9 of 13

AC Electrical Specification

The AC Electrical specifications follow. [6]

Parameter Description Min Typ Max Unit

tCYCLE Clock Cycle time[19] 1.25 3.34 ns

tJIT(cc) Jitter over 1-6 clock cycles at 400–635 MHz[20] –2540ps

Jitter over 1-6 clock cycles at 638–667 MHz – 25 30 ps

L20 Phase noise SSB spectral purity L(f) at 20 MHz offset: 400–500 MHz

(In addition, device must not exceed L(f) = 10log[1+(50x106/f)2.4] –138 for

f = 1 MHz to 100 MHz except for the region near f = REFCLK/Q where Q is

the value of the internal reference divider.)

– –135 –128 dBC/Hz

tJIT(hper,cc) Cycle-to-cycle duty cycle error at 400–635 MHz – 25 40 ps

Cycle-to-cycle duty cycle error at 636–667 MHz – 25 30 ps

ΔtSKEW Drift in tSKEW when ambient temperature varies between 0°C and 70°C and

supply voltage varies between 2.375V and 2.625V.[21] ––15ps

DC Long term average output duty cycle 45% 50 55% tCYCLE

tEER,SCC PLL output phase error when tracking SSC –100 – 100 ps

tCR,tCF Outputriseandfalltimesat400–667 MHz (measuredat20%–80%ofoutput

voltage) –150–ps

tCR,CF Difference between output rise and fall times on the same pin of the single

device (20%–80%) of 400–667 MHz[22] – – 100 ps

Table 9. SMBus Timing Specification

Parameter Description Min Max Units

FSMB SMBus Operating Frequency 10 100 kHz

TBUF Bus free time between Stop and Start Condition 4.7 μs

THD:STA Hold time after (Repeated) Start Condition.

After this period, the first clock is generated. 4.0 μs

TSU:STA Repeated Start Condition setup time 4.7 μs

TSU:STO Stop Condition setup time 4.0 μs

THD:DAT Data Hold time 0 ns

TSU:DAT Data Setup time 250 ns

TTIMEOUT Detect clock low timeout Not supported

TLOW Clock low period 4.7 μs

THIGH Clock high period 4.0 50 μs

TLOW:SEXT Cumulative clock low extend time (slave device) 25 ms

CY24272 doesn’t

extend

TLOW:MEXT Cumulative clock low extend time (master device) 10 ms

TF Clock/Data Fall Time 300 ns

TR Clock/Data Rise Time 1000 ns

TPOR Time in which a device must be operational after power on reset 500 ms

[+] Feedback

CY24272

Document Number: 001-42414 Rev. ** Page 10 of 13

Test and Measurement Setup

Figure 3. Clock Outputs

Signal Waveforms

A physical signal that appears at the pins of a device is deemed

valid or invalid depending on its voltage and timing relations with

other signals. Input and output voltage waveforms are defined as

showninFigure 4on page 11. Both rise andfalltimes aredefined

between the 20% and 80% points of the voltage swing, with the

swing defined as VH–VL.

Figure 5 on page 11 shows the definition of the output crossing

point. The nominal crossing point between the complementary

outputs is defined as the 50% point of the DC voltage levels.

There are two crossing points defined: Vx+ at the rising edge of

CLK and Vx– at the falling edge of CLK. For some waveforms,

both Vx+ and Vx– are below Vx,nom (for example, if tCR is larger

than tCF).

Jitter

This section defines the specifications that relate to timing uncer-

tainty (or jitter) of the input and output waveforms. Figure 6 on

page 11 shows the definition of cycle-to-cycle jitter with respect

to the falling edge of the CLK signal. Cycle-to-cycle jitter is the

differencebetweencycletimesofadjacentcycles.Equalrequire-

ments apply rising edges of the CLK signal. Figure 7 on page 11

shows the definition of cycle-to-cycle duty cycle error (tDC,ERR).

Cycle-to-cycle duty cycle is defined as the difference between

tPW+ (high times) of adjacent differential clock cycles. Equal

requirements apply to tPW-, low times of the differential click

cycles.

Differential Driver

CLK

CLKB

Swing Current

Control

ISET

RRC

Measurement

Point

VTS

R1ZCH

RT1

CSRT2

Measurement

Point

VTS

R1ZCH

RT1

CSRT2

Notes

19.Max and min output clock cycle times are based on nominal outputs frequency of 300 and 667 MHz, respectively. For spread spectrum modulated differential or

single-ended REFCLK, the output clock tracks the modulation of the input.

20.Output short term jitter spec is the absolute value of the worst case deviation.

21.tSKEW is the timing difference between any two of the four differential clocks and is measured at common mode voltage. ΔtSKEW is the change in tSKEW when the

operating temperature and supply voltage change.

22.tCR,CF applies only when appropriate RRC and output resistor network resistor values are selected to match pull up and pull down currents.

Example External Resistor Values

and Termination Voltages for a 50ΩChannel

Parameter Value Unit

R133.0 Ω

R218.0 Ω

R317.0 Ω

RT1 60.4 Ω

RT2 301 Ω

CS2700 pF

RRC 432 Ω

VTS 2.5V V

VT1.2V V

[+] Feedback

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