Cypress CY62167EV18 Manuale utente

CY62167EV18 MoBL®

16 Mbit (1M x 16) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05447 Rev. *G Revised March 13, 2009

Features

■Very high speed: 55 ns

■Wide voltage range: 1.65V to 2.25V

■Ultra low standby power

❐Typical standby current: 1.5 μA

❐Maximum standby current: 12 μA

■Ultra low active power

❐Typical active current: 2.2 mA at f = 1 MHz

■Easy memory expansion with CE1, CE2, and OE features

■Automatic power down when deselected

■CMOS for optimum speed and power

■Offered in Pb-free 48-ball VFBGA packages

Functional Description

The CY62167EV18 is a high performance CMOS static RAM

organized as 1M words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™(MoBL®) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that reduces power consumption

by 99 percent when addresses are not toggling. Place the device

into standby mode when deselected (CE1HIGH or CE2 LOW or

both BHE and BLE are HIGH). The input and output pins (I/O0

through I/O15) are placed in a high impedance state when: the

device is deselected (CE1HIGH or CE2LOW); outputs are

disabled (OE HIGH); both Byte High Enable and Byte Low

Enable are disabled (BHE, BLE HIGH); and a write operation is

in progress (CE1LOW, CE2HIGH and WE LOW).

To write to the device, take Chip Enables (CE1 LOW and CE2

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O0through I/O7) is

written into the location specified on the address pins (A0through

A19). If Byte High Enable (BHE) is LOW, then data from I/O pins

(I/O8through I/O15) is written into the location specified on the

address pins (A0through A19).

To read from the device, take Chip Enables (CE1 LOW and CE2

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appears

on I/O0to I/O7. If Byte High Enable (BHE) is LOW, then data from

memory appears on I/O8to I/O15. See the Truth Table on page

9for a complete description of read and write modes.

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

PowerDown

Circuit BHE

BLE

CE2

CE1

1M × 16

RAM ARRAY IO0–IO7

ROW DECODER

A 8

A 7

A 6

A 5

A 2

COLUMN DECODER

A11

A12

A13

A14

A15

SENSE AMPS

DATA IN DRIVERS

A 4

A 3IO8–IO15

BLE

BHE

A16

A 0

A 1

A17

A 9

A18

A10

CE2

CE1

A19

Logic Block Diagram

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CY62167EV18 MoBL®

Document #: 38-05447 Rev. *G Page 2 of 13

Pin Configuration

Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View [1, 2, 3]

Product Portfolio

Product VCC Range (V) Speed

(ns)

Power Dissipation

Operating ICC (mA)

Standby ISB2 (μA)

f = 1 MHz f = fmax

Min Typ[4] Max Typ[4] Max Typ[4] Max Typ[4] Max

CY62167EV18LL 1.65 1.8 2.25 55 2.2 4.0 25 30 1.5 12

CY62167EV30LL[5]

A11

A10

A3CE1

IO10

IO8

IO9

IO13

IO12

IO14

IO15

Vss

IO0

BHE

CE2

A17

BLE

IO2

IO1

IO4

IO5IO6

IO7

A15

A14

A13

A19

A18

A16

Vcc

Notes

1. The information related to 6 x 7 x 1 mm VFBGA package is preliminary.

2. NC pins are not connected on the die.

3. Ball H6 for the VFBGA package can be used to upgrade to a 32M density.

4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.

5. This part can be operated in the VCC range of 1.65V–2.25V at 55ns speed. It can also be operated in the VCC range of 2.2V–3.6V at 45ns speed.

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CY62167EV18 MoBL®

Document #: 38-05447 Rev. *G Page 3 of 13

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with

Power Applied ........................................... –55°C to + 125°C

Supply Voltage to Ground

Potential .......................... –0.2V to 2.45V (VCC(max) + 0.2V)

DC Voltage Applied to Outputs

in High Z State[6, 7]........... –0.2V to 2.45V (VCC(max) + 0.2V)

DC Input Voltage[6, 7] ....... –0.2V to 2.45V (VCC(max) + 0.2V)

Output Current into Outputs (LOW) ............................ 20 mA

Static Discharge Voltage........................................... >2001V

(MIL-STD-883, Method 3015)

Latch up Current...................................................... >200 mA

Operating Range

Device Range Ambient

Temperature VCC[8]

CY62167EV18LL Industrial –40°C to +85°C 1.65V to 2.25V

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions 55 ns Unit

Min Typ[4] Max

VOH Output HIGH Voltage IOH = –0.1 mA 1.4 V

VOL Output LOW Voltage IOL = 0.1 mA 0.2 V

VIH Input HIGH Voltage VCC = 1.65V to 2.25V 1.4 VCC + 0.2V V

VIL Input LOW Voltage VCC = 1.65V to 2.25V –0.2 0.4 V

IIX Input Leakage Current GND < VI< VCC –1 +1 μA

IOZ Output Leakage Current GND < VO <VCC, Output Disabled –1 +1 μA

ICC VCC Operating Supply

Current

f = fmax = 1/tRC VCC = VCC(max)

IOUT = 0 mA

CMOS levels

25 30 mA

f = 1 MHz 2.2 4.0 mA

ISB1 Automatic CE Power Down

Current – CMOS Inputs

CE1> VCC – 0.2V or CE2 <0.2V

VIN >VCC – 0.2V, VIN <0.2V)

f = fmax(Address and Data Only),

f = 0 (OE, WE, BHE and BLE),

VCC = VCC(max)

1.5 12 μA

ISB2[9] Automatic CE Power Down

Current – CMOS Inputs

CE1> VCC – 0.2V or CE2< 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V,

f = 0, VCC = VCC(max)

1.5 12 μA

Capacitance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = VCC(typ)

10 pF

COUT Output Capacitance 10 pF

Notes

6. VIL(min) = –2.0V for pulse durations less than 20 ns.

7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.

8. Full Device AC operation is based on a 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization.

9. Only chip enables (CE1 and CE2), and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.

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CY62167EV18 MoBL®

Document #: 38-05447 Rev. *G Page 4 of 13

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions VFBGA

(6 x 7 x 1mm)

VFBGA

(6 x 8 x 1mm) Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Still air, soldered on a 3 × 4.5 inch,

two-layer printed circuit board

27.74 55 °C/W

ΘJC Thermal Resistance

(Junction to Case)

9.84 16 °C/W

Figure 2. AC Test Loads and Waveforms

Parameters 1.8V Unit

R1 13500 Ω

R2 10800 Ω

RTH 6000 Ω

VTH 0.80 V

Data Retention Characteristics

Over the Operating Range

Parameter Description Conditions Min Typ[4] Max Unit

VDR VCC for Data Retention 1.0 V

ICCDR[9] Data Retention Current VCC = 1.0V, CE1> VCC – 0.2V, CE2< 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V

10 μA

tCDR[10] Chip Deselect to Data

Retention Time

0ns

tR[11] Operation Recovery Time tRC ns

Figure 3. Data Retention Waveform

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10% 90%

10%

Rise Time = 1 V/ns Fall Time = 1 V/ns

OUTPUT V

Equivalent to: THÉVENIN EQUIVALENT

ALL INPUT PULSES

RTH

Notes

10. Tested initially and after any design or process changes that may affect these parameters.

11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.

12. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.

VCC(min)

tCDR

VDR >1.0 V

DATA RETENTION MODE

CE1or

VCC

BHE.BLE

CE2

[12]

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CY62167EV18 MoBL®

Document #: 38-05447 Rev. *G Page 5 of 13

Switching Characteristics

Over the Operating Range[13, 14]

Parameter Description 55 ns Unit

Min Max

Read Cycle

tRC Read Cycle Time 55 ns

tAA Address to Data Valid 55 ns

tOHA Data Hold from Address Change 10 ns

tACE CE1LOW and CE2 HIGH to Data Valid 55 ns

tDOE OE LOW to Data Valid 25 ns

tLZOE OE LOW to Low-Z[15] 5ns

tHZOE OE HIGH to High-Z[15, 16] 18 ns

tLZCE CE1LOW and CE2 HIGH to Low-Z[15] 10 ns

tHZCE CE1HIGH and CE2 LOW to High-Z[15, 16] 18 ns

tPU CE1LOW and CE2 HIGH to Power Up 0 ns

tPD CE1HIGH and CE2 LOW to Power Down 55 ns

tDBE BLE/BHE LOW to Data Valid 55 ns

tLZBE BLE/BHE LOW to Low-Z[15] 10 ns

tHZBE BLE/BHE HIGH to High-Z[15, 16] 18 ns

Write Cycle[17]

tWC Write Cycle Time 55 ns

tSCE CE1LOW and CE2 HIGH to Write End 40 ns

tAW Address Setup to Write End 40 ns

tHA Address Hold from Write End 0 ns

tSA Address Setup to Write Start 0 ns

tPWE WE Pulse Width 40 ns

tBW BLE/BHE LOW to Write End 40 ns

tSD Data Setup to Write End 25 ns

tHD Data Hold from Write End 0 ns

tHZWE WE LOW to High-Z[15, 16] 20 ns

tLZWE WE HIGH to Low-Z[15] 10 ns

Notes

13. Test conditions for all parameters other than tri-state parameters are based on signal transition time of 1V/ns, timing reference levels of VCC(typ)/2, input pulse levels

of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 4.

14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.

15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given

device.

16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state.

17. The internal memory write time is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and

any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

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CY62167EV18 MoBL®

Document #: 38-05447 Rev. *G Page 6 of 13

Switching Waveforms

Figure 4 shows address transition controlled read cycle waveforms.[18, 19]

Figure 4. Read Cycle No. 1

Figure 5 shows OE controlled read cycle waveforms.[19, 20]

Figure 5. Read Cycle No. 2

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tPD

tHZBE

tLZBE

HZCE

tDBE

CE1

ADDRESS

CE2

BHE/BLE

DATA OUT

VCC

SUPPLY

CURRENT

HIGH

ICC

ISB

IMPEDANCE

Notes

18. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.

19. WE is HIGH for read cycle.

20. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2transition HIGH.

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CY62167EV18 MoBL®

Document #: 38-05447 Rev. *G Page 7 of 13

Figure 6 shows WE controlled write cycle waveforms.[17, 21, 22]

Figure 6. Write Cycle No. 1

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

NOTE 23

CE1

ADDRESS

CE2

DATA I/O

BHE/BLE

Notes

21. Data IO is high impedance if OE = VIH.

22. If CE1goes HIGH and CE2goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

23. During this period the IOs are in output state. Do not apply input signals.

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CY62167EV18 MoBL®

Document #: 38-05447 Rev. *G Page 8 of 13

Figure 7 shows CE1or CE2controlled write cycle waveforms.[17, 21, 22]

Figure 7. Write Cycle No. 2

Figure 8 shows WE controlled, OE LOW write cycle waveforms.[22]

Figure 8. Write Cycle No. 3

Switching Waveforms (continued)

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

tSA

NOTE 23

CE1

ADDRESS

CE2

DATA I/O

BHE/BLE

VALID DATA

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

tBW

NOTE 23

ADDRESS

DATA I/O

BHE

/BLE

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CY62167EV18 MoBL®

Document #: 38-05447 Rev. *G Page 9 of 13

Figure 9 shows BHE/BLE controlled, OE LOW write cycle waveforms.[22]

Figure 9. Write Cycle No. 4

Truth Table

CE1CE2WE OE BHE BLE Inputs/Outputs Mode Power

HXXXXXHighZ Deselect/PowerDown Standby (ISB)

XLXXXXHighZ Deselect/PowerDown Standby (ISB)

XXXXHHHighZ Deselect/PowerDown Standby (ISB)

L H H L L L Data Out (I/O0–I/O15) Read Active (ICC)

L H H L H L Data Out (I/O0–I/O7);

High Z (I/O8–I/O15)

Read Active (ICC)

LHHLLHHighZ(I/O

0–I/O7);

Data Out (I/O8–I/O15)

Read Active (ICC)

L H H H L H High Z Output Disabled Active (ICC)

LHHHHLHighZ OutputDisabled Active(I

CC)

L H H H L L High Z Output Disabled Active (ICC)

L H L X L L Data In (I/O0–I/O15) Write Active (ICC)

L H L X H L Data In (I/O0–I/O7);

High Z (I/O8–I/O15)Write Active (ICC)

LHLXLHHighZ(I/O

0–I/O7);

Data In (I/O8–I/O15)

Write Active (ICC)

Switching Waveforms (continued)

tHD

tSD

tSA

tHA

tAW

tWC

VALID DATA

tBW

tSCE

tPWE

NOTE 23

ADDRESS

DATA IO

BHE

/BLE

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CY62167EV18 MoBL®

Document #: 38-05447 Rev. *G Page 10 of 13

Ordering Information

Speed

(ns) Ordering Code

Package

Diagram Package Type Operating

Range

55 CY62167EV18LL-55BAXI 001-13297 48-ball VFBGA (6 × 7 × 1 mm) (Pb-free) Industrial

CY62167EV18LL-55BVI 51-85150 48-ball VFBGA (6 × 8 × 1 mm)

CY62167EV18LL-55BVXI 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free)

CY62167EV30LL-45BVI [5] 51-85150 48-ball VFBGA (6 × 8 × 1 mm)

Package Diagram

Figure 10. 48-Ball VFBGA (6 x 7 x 1 mm), 001-13297

NOTES:

1. ALL DIMENSION ARE IN MM [MAX/MIN]

2. JEDEC REFERENCE : MO-216

3. PACKAGE WEIGHT : 0.03g 001-13297-*A

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