Cypress EZ-USB CX3 Manuale del prodotto

EZ-USB® CX3 Technical Reference Manual

(Supplement to the EZ-USB FX3 Technical Reference Manual)

Doc. No. 001-91492 Rev. *B

EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 2

Cypress EZ-USB CX3

1.1 Introduction

Cypress EZ-USB®CX3 is a USB 3.0 camera controller that enables developers to add USB 3.0 connectivity

to any image sensors conforming to the Mobile Industry Processor Interface (MIPI) Camera Serial Interface

Type 2 (CSI-2) standard. It serves as a MIPI CSI-2-to-USB Bridge.

EZ-USB CX3 is a variant of the EZ-USB FX3 device that features an integrated MIPI CSI-2 receiver mated to

the general programming interface II (GPIF II). CX3 provides the ability to add SuperSpeed USB connectivity

to image sensors supporting the MIPI CSI-2 interface.

CX3 conforms to the MIPI CSI-2 specification (version 1.01) and supports up to four data lanes with speed up

to 1 gigabits per second (Gbps) per lane for a total bandwidth of 2.4 Gbps.

CX3 is ideally suited forhigh-definition or high-speed image capturing applications and is capable of streaming

uncompressed video up to 1080p at 30 fps or 720p at 60 fps. CX3 supports a wide variety of image formats

including RAW8/10/12/14, YUV422, RGB888/666/565, and user-defined 8-bit.

Figure 1: EZ-USB® CX3 Device

Based on the proven EZ-USB FX3 platform, CX3 includes an ARM9™CPU and 512 KB SRAM that provide

200 MIPS of computational power. CX3 supports multiple peripheral interfaces such as I2C, SPI, and UART,

which can be programmed to support Autofocus, Pan, Tilt, and Zoom (PTZ), or other camera control functions.

CX3 uses the same application development tools as FX3. The FX3 Software Development Kit provides

support for CX3 along with application examples for accelerating time to market. CX3 complies with the USB

3.0 v1.0 specification and therefore is backward compatible with USB 2.0.

This technical reference manual (TRM) is a supplement to the EZ-USB FX3 TRM, and provides details about

the added CX3 MIPI CSI-2 receiver function block. Sections 1.5 through 1.9 of this TRM supplement describe

the MIPI CSI-2 receiver functional block, including the fixed-function GPIF II state machine. Section 1.10

provides the register details for the MIPI CSI-2 receiver interface. Detailed descriptions of the existing FX3

Cypress EZ-USB CX3

EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 3

functional blocks, such as the CPU Subsystem, Memory, Global Controller, DMA, USB, and low-bandwidth

(serial and GPIO) peripherals are available in the EZ-USB FX3 TRM. Technical terms used in this TRM are

defined in the Glossary.

Figure 2 is the block diagram of FX3. Certain functional blocks are not included in CX3; these are shown in

red. The GPIF II, shown in blue, is included in CX3, but only with functionality specific to the camera interface.

Figure 2: FX3 Block Diagram

UART SPI I2S

I2C

GPIF II 32

EPs

HS/FS/LS

OTG Host

Peripheral

HS/FS

Peripheral

Charger

Detection

(EZ-Dtect™)

USB Interface

ARM926EJ-S

JTAG

System

RAM

I2C_SDA

I2C_SCL

D+

D-

SSTX+

SSTX-

SSRX+

SSRX-

OTG_ID

FX3 BLOCK DIAGRAM

Memory

Controller

GPIOs

Not Available in CX3

Limited Functionality in CX3

Available in CX3

Figure 3 shows the CX3 block diagram, including the added MIPI CSI-2 functional block and the fixed-function

GPIF II interface available in CX3, highlighted in green.

Figure 3: CX3 Block Diagram

UART SPI I2S

I2C

Fixed

Function

GPIF II

EPs

Peripheral

HS/FS

Peripheral

USB Interface

ARM926EJ-S

JTAG

System

RAM

D+

D-

SSTX+

SSTX-

SSRX+

SSRX-

CX3 BLOCK DIAGRAM

Memory

Controller

MIPI

CSI-2

Receiver

Block

I2C_SDA

I2C_SCL

MIPI

CSI2

Input

Image

Sensor

USB

Host

MCLK

XRESET

XSHUTDOWN

GPIOs

New Functionality in CX3

Cypress EZ-USB CX3

EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 4

The differences between CX3 and FX3 devices are listed below.

Table 1: Differences Between FX3 and CX3 Devices

Feature

Supported in FX3

Supported in CX3

P-Port Support

Sync ADMux implemented with GPIF II

Yes

Async SRAM implemented with GPIF II

Yes

Async ADMux implemented with GPIF II

Yes

MMC Slave

Yes

GPIF II

Yes

Fixed-function GPIF II state

machine implemented to interface

with the CX3 MIPI CSI-2 receiver

block.

Low-Bandwidth Peripherals

I2S Master (Transmitter only)

Yes

SPI Master

Yes

UART

Yes

I2C Master Controller

Yes

U-Port Support

USB 3.0 Peripheral

Yes

USB 2.0 Peripheral

Yes

32 Physical endpoints

Yes

Charger Detection 1.1 Support (EZ-Dtect™)

Yes

Accessory Charger Adaptor (ACA) Support

Yes

Integrated Hi-Speed USB Switch

Yes

Carkit UART Pass-through mode

Yes

USB OTG (Hi-Speed, Full-Speed, Low-Speed host or

peripheral)

Yes

Clock input frequencies:

19.2 MHz,

26 MHz,

38.4 MHz,

52 MHz

19.2 MHz

Crystal input: 19.2 MHz

Yes

JTAG Support for debug only (Boundary Scan not

supported)

Yes

VBUS, VBAT signals

Separate VBUS, VBAT

signals for 5-V and

3.3-V operation

VBUS, VBAT combined to a

single signal VUSB. Supports 3.3-

V and 5-V operation.

GPIOs

Clock output for Image sensor

Yes

MIPI CSI-2 input

Yes

Cypress EZ-USB CX3

EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 5

1.2 CX3 Features

CX3 supports the following features:

▪USB 3.0 and USB 2.0 peripheral controller compliant with the USB 3.0 specification 1.0

▪MIPI CSI-2 RX Interface

oMIPI CSI-2 conformant (Version 1.01 Revision 0.04 –April 2, 2009)

oSupports up to four data lanes; each lane supports up to 1 Gbps

oCamera Control Interface (over I2C) support for image sensor configuration

▪Supports the following video data formats:

oRAW 8/10/12/14

oYUV 422 (8/10bit)

oRGB 888 / 666 / 565

oUser-defined 8-bit

▪Twelve GPIOs for controlling camera-related functions (for example, lighting, sync in, sync out, etc.)

▪Support for I2C, SPI, I2S outputs, and UART interfaces, identical to FX3

▪JTAG interface for debugging

Cypress EZ-USB CX3

EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 6

1.3 Block Diagram

Figure 4 is a detailed block diagram of a typical system using CX3 to transfer data from an image

sensor to a USB Host.

Figure 4: System Block Diagram

Image Sensor

Video

Data

Video

Control

USB Host

Host

Application

UVC/

Custom

Driver

USB

Host

Controller

GPIO

Fixed

Function

GPIF II

I2C

Master

UIB

CX3

DMA

Channel

USB

Bulk

IN EP

USB

EP0

Video

Data

Firmware

Data

Lanes

Clock

Lane

Other I/O

Sensor-

Specific I/O

The main sub-blocks of the block diagram are numbered, and the tasks executed by each sub-block are

described below:

1. The MIPI CSI-2-based image sensor connects to CX3 and is configured using the Camera Control

Interface (I2C) bus.

2. The CX3 MIPI CSI-2 receiver block reads the data from the image sensor, de-serializes it, merges lanes,

de-packetizes it, and then sends it as a parallel input to the fixed function GPIF II block.

3. The GPIF II block and its fixed-function state machine make the image sensor data available to the USB

interface using a DMA channel.

4. The DMA channel moves the image data from the GPIF II block to the USB Interface Block (UIB).

5. The CX3 firmware initializes the CX3 hardware blocks, configures the image sensor and MIPI CSI-2

controller, controls the USB interface, and services all USB protocol requests. The CX3 firmware can be

customized to add class-specific headers to the video stream data before it is committed to the USB

interface.

6. A host application such as an image signal processor or a video stream player provides control requests

to configure the video stream and sensor, and processes and renders the video stream on the host PC.

Cypress EZ-USB CX3

EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 7

1.4 MIPI CSI-2 Block Configuration APIs

The MIPI CSI-2 Rx-block configuration APIs allow user applications to initialize, configure, and perform power

management for the camera interface. These APIs communicate with the camera over the I2C bus.

For modularity, the MIPI CSI-2 configuration APIs are compiled into a separate API library (cyu3mipicsi.a).

This library is linked with the application only if its functionality is required.

The main APIs provided in the API library are as follows:

Table 2: CX3-Specific APIs in the EZ-USB FX3 SDK

API Name

API Description

CyU3PMipicsiInit()

API to initialize the MIPI CSI-2 block.

CyU3PMipicsiDeInit()

API to de-initialize the MIPI CSI-2 block.

CyU3PMipicsiSetIntfParams()

API to configure the clocks and interface settings on the MIPI CSI-2

block.

CyU3PMipicsiQueryIntfParams()

API to query settings from the MIPI CSI-2 block.

CyU3PMipicsiSleep()

API to place the MIPI CSI-2 block in the low-power sleep mode.

CyU3PMipicsiWakeup()

API to wake the MIPI CSI-2 block from the low-power sleep mode to

active mode.

CyU3PCx3DeviceReset()

API to reset the MIPI CSI-2 block.

CyU3PCx3DeviceReset()

API to perform a warm or cold reset on the CX3 device.

CyU3PMipicsiSetSensorControl()

API to drive the MIPI CSI-2 XRESET and XSHUTDOWN signals to the

image sensor.

XRESET is a CX3 output signal that can be used to reset the image

sensor.

XSHUTDOWN is a CX3 output signal that can be used to control

image sensor power modes.

CyU3PMipicsiGpifLoad()

API to load the fixed-function GPIF II waveform and configure the

fixed-function GPIF II bus widths and DMA buffer size.

More information on the APIs is available in Section 1.11

Detailed API documentation is available in the MIPI CSI-2 and Fixed-Function GPIF Interface for CX3 section

of the EZ-USB FX3 SDK Firmware API Guide, available as part of the EZ USB FX3 SDK.

Cypress EZ-USB CX3

EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 8

1.5 MIPI CSI-2 Block

The CX3 device has an integrated MIPI CSI-2 block, which is hard-wired to the GPIF II interface on one side

and provides a MIPI CSI-2 interface on the other side to interface to an image sensor that supports MIPI CSI-

2. The block supports up to four MIPI CSI-2 data lanes, and is capable of speeds up to 1 Gbps per lane. The

MIPI CSI-2 receiver is connected to a fixed-function GPIF II controller via an 8-, 16-, or 24-bit data bus, which

can be clocked up to100 MHz. The maximum bandwidth thatcan be achieved is 2.4Gbps (i.e. 24 * 100 Mbps).

The MIPI CSI-2 block is configured over I2C and is available on the CX3 I2C bus at the 7-bit I2C slave address

7’b0000111.

Figure 5. CX3 MIPI CSI-2 Block

I2C

Fixed-Function

GPIF II

MIPI CSI-2

Block

8/16/24-Bit

Interface

I2C_SDA

I2C_SCL

1/2/3/4 Lane

MIPI CSI-2

Input

I2C Address

7’b0000111

XRESET

MCLK

XSHUTDOWN

REFCLK

MIPI CSI-2

Receiver

Parallel

Output

Cypress EZ-USB CX3

EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 9

1.6 CX3 MIPI CSI-2 Stream Formats

The MIPI CSI-2 Rx block on CX3 natively supports the following stream formats and output modes:

Table 3: CX3 MIPI CSI-2 Stream Formats

Format and

Mode

CX3 Firmware Stream Format

Name

Format

Description,

Pixel Depth

CSI-2

Data

Typea

GPIF II

Bus Width

Output Stream

RAW8

CY_U3P_CSI_DF_RAW8

RAW format,

8 bits per pixel

0x2A

8-bit

RAW [7:0]

RAW10

CY_U3P_CSI_DF_RAW10

RAW format,

10 bits per

pixel

0x2B

16-bit

6’b0, RAW [9:0]

RAW12

CY_U3P_CSI_DF_RAW12

RAW format,

12 bits per

pixel

0x2C

16-bit

4’b0, RAW [11:0]

RAW14

CY_U3P_CSI_DF_RAW14

RAW format,

14 bits per

pixel

0x2D

16-bit

2'b0,RAW[13:0]

RGB888

CY_U3P_CSI_DF_RGB888

RGB 888

format,

24 bits per

pixel

0x24

24-bit

R[7:0], G[7:0],

B[7:0]

RGB666 Mode 0

CY_U3P_CSI_DF_RGB666_0

RGB 666

format,

24 bits per

pixel

0x23

24-bit

2’b0, R[5:0], 2’b0,

G[5:0], 2’b0,

B[5:0]

RGB666 Mode 1

CY_U3P_CSI_DF_RGB666_1

RGB 666

format,

24 bits per

pixel

0x23

24 bit

6’b0, R[5:0],

G[5:0], B[5:0]

RGB565 Mode 0

CY_U3P_CSI_DF_RGB565_0

RGB 565

format,

24 bits per

pixel

0x22

24-bit

2’b0, R[4:0],

3’b0, G[5:0],

2’b0, B[4:0], 1’b0

RGB565 Mode 1

CY_U3P_CSI_DF_RGB565_1

RGB 565

format,

24 bits per

pixel

0x22

24-bit

3’b0, R[4:0],

2’b0, G[5:0],

3’b0,B[4:0]

RGB565 Mode 2

CY_U3P_CSI_DF_RGB565_2

RGB 565

format,

16 bits per

pixel

0x22

16-bit

R[4:0], G[5:0],

B[4:0]

YUV422

8-bit Mode 0

CY_U3P_CSI_DF_YUV422_8_0

YUV422 format

16 bits per

pixel

0x1E

8-bit

P[7:0]

Data Order:

U1,Y1,V1,Y2,U3,

Y3,..

MIPI CSI-2 defined Data Type code. Please refer to the MIPI CSI-2 specification for details.

Cypress EZ-USB CX3

EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 10

Format and

Mode

CX3 Firmware Stream Format

Name

Format

Description,

Pixel Depth

CSI-2

Data

Typea

GPIF II

Bus Width

Output Stream

YUV422

8-bit Mode 1

CY_U3P_CSI_DF_YUV422_8_1

YUV422 format

16 bits per

pixel

0x1E

16-bit

P[15:0]

Data Order:

{U1,Y1},{V1,Y2},{

U3, Y3},{V3,Y4}...

YUV422

8-bit Mode 2

CY_U3P_CSI_DF_YUV422_8_2

YUV422 format

16 bits per

pixel

0x1E

16-bit

P[15:0]

Data Order:

{Y1,U1},{Y2,V1},{

Y3,

U3},{Y4,V3}....

YUV422

10-bit

CY_U3P_CSI_DF_YUV422_10

YUV422 format

20 bits per

pixel

0x1F

16-bit

6'b0,P[9:0]

Data Order:

U1,Y1,V1,Y2,U3,

Y3, V3,Y4.

MIPI CSI-2 defined Data Type code. Please refer to the MIPI CSI-2 specification for details.

If the GPIF II bus width selected is larger than the width of the output stream, for example if a 24-bit GPIF II

bus width is used for the CY_U3P_CSI_DF_YUV422_8_1 type, the upper bits on the GPIF II are padded with

0s.

For stream formats not listed in Table 3, such as MJPEG or custom format streams, 8 bit wide streams can

be transported on the RAW8 stream format, and 24 bit wide streams can be transported by treating the stream

as an RGB888 format stream. GPIF bus widths and buffers should be set up appropriately to match the stream

output. Section 1.11.12 has more details on setting up the GPIF bus-width and DMA buffers.

Packing more than one pixel per PCLK is possible. For example, selecting the “MIPI CSI input -Data format"

configured as "RAW8" and the “MIPI interface configuration –data format” as a 24bit format (RGB888) will

output three pixel data per PCLK. Similarly, two 10 bit or 12bit pixels can be packed and output per PCLK

using the 24 bit output format.

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