HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
© 2014 Dialog Semiconductor GmbH
www.dialog-semiconductor.com
Tables
Table 1: DA6021 Absolute Maximum Ratings............................................................................................ 19
Table 2: DA6021 Recommended Operating Conditions............................................................................ 19
Table 3: Abbreviations of Validation Status................................................................................................ 20
Table 4: Pin Description.............................................................................................................................. 25
Table 5: Pin Type Definition........................................................................................................................ 25
Table 6 : G3 State Transition...................................................................................................................... 31
Table 7: SOC_G3 State Transition............................................................................................................. 31
Table 8:SOC S0 State Transition ............................................................................................................... 33
Table 9: SOC S0iX State Transition........................................................................................................... 34
Table 10: SOC S3 State Transition ............................................................................................................ 34
Table 11: SOC S4 State Transition ............................................................................................................ 35
Table 12: Truth Table of Sleep Signals and DA6021 Final Power States.................................................. 35
Table 13: DA6021 State Transition and Sleep Signals .............................................................................. 36
Table 14: Slave ID versus DA6021 Storage Page ..................................................................................... 37
Table 15:U2 & D2 Event Generation Table................................................................................................ 39
Table 16: Cold Boot Triggers...................................................................................................................... 42
Table 17: Truth Table of Cold Boot Triggers.............................................................................................. 42
Table 18: Cold Boot Timings...................................................................................................................... 45
Table 19: Enter S0iX timing........................................................................................................................ 49
Table 20: Exit S0iX timing........................................................................................................................... 52
Table 21: Cold Off Triggers ........................................................................................................................ 57
Table 22: Cold Off Sequencing Timing....................................................................................................... 61
Table 23: Catastrophic Event (except VSYSOVP) Shutdown Sequence .................................................. 63
Table 24: VSYSOVP Shutdown Timing...................................................................................................... 63
Table 25: Modem Reset Timing Intervals................................................................................................... 64
Table 26 : PMIC Reset Sources................................................................................................................. 65
Table 27: Power Domains .......................................................................................................................... 67
Table 28: Status Power Domains............................................................................................................... 68
Table 29: PMIC Current Consumption ....................................................................................................... 68
Table 30: VCC & VNN Addresses.............................................................................................................. 69
Table 31: SVID DC Electrical Characteristics............................................................................................. 69
Table 32: SVID buffer AC Electrical Parameters........................................................................................ 70
Table 33: VCLK AC Timing Parameters..................................................................................................... 70
Table 34: SVID Supported Commands...................................................................................................... 73
Table 35: SVID Supported Registers ......................................................................................................... 75
Table 36: VID Values.................................................................................................................................. 78
Table 37: Electrical Parameters for BUCK_VCC ....................................................................................... 81
Table 38: Electrical Parameters for BUCK_VNN ....................................................................................... 83
Table 39: Electrical Parameter for BUCK_V1P0A...................................................................................... 85
Table 40: V1P0A Truth Table..................................................................................................................... 87
Table 41: V1P0S_EN Truth Table.............................................................................................................. 87
Table 42: V1P0SX_EN Truth Table............................................................................................................ 88
Table 43: VDDQ_VTT Truth Table............................................................................................................. 89
Table 44: Electrical Parameter for VDDQ_VTT.......................................................................................... 89
Table 45: Electrical Parameter for BUCK_V1P05S.................................................................................... 90
Table 46: V1P05S Truth Table................................................................................................................... 92
Table 47: Electrical Parameter for BUCK_V1P8A...................................................................................... 93
Table 48: V1P8A Truth Table..................................................................................................................... 94
Table 49: V1P8U_EN_B Truth Table ......................................................................................................... 95
Table 50: V1P8S Power Switch Specification............................................................................................ 95
Table 51: V1P8S Truth Table..................................................................................................................... 95
Table 52: V1P8S Power Switch Specification............................................................................................ 96
Table 53: V1P8SX Truth Table................................................................................................................... 96
Table 54: Electrical Parameter for V1P2A.................................................................................................. 97
Table 55: Electrical Parameter for VREFDQ1/2......................................................................................... 98
Table 56: Electrical Parameter for BUCK_VDDQ ...................................................................................... 99
