Digital Equipment PDP-9 Guida

(

Digital

Equipment

Corporation

Maynard, Massachusetts

PDP-9

momODma

DEC-9A-HOAA-D

PDP-9

SYSTEM

ADJUSTMENT

MANUAL

DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS

1st Printing November 1968

2nd Printing November 1969

The following

are

trademarks

Digital Equip-

ment

Corporation,

Maynard,

Massachusetts:

DEC

FLIP

CHIP

DIGITAL

PDP

FOCAL

COMPUTER

LAB

CONTENTS

Page

1. Introduction

Main Memory

(MM)

2.1

MC70B

Voltage Checks and Adjustments

2.1.1

Main Voltage Check

2.1.2

Second Stage Clamp Voltage Check

2.1.3

Slice Voltage Check

2.2

MC70B

Timing Adjustments 2

2.2.1

Check 2

2.2.2

Set

2.2.3

Procedures 3

Control Memory (CM) 9

3.1

Check 10

3.2

Set

3.3

Procedures

3.3.1

Current Start Delay

3.3.2

Start Delay

"3.3.3

Width Delay

3.3.4

Loop

Delay 14

3.3.5

Strobe Start Delay

3.3.6

CLR

Position Delay

3.3.7

Current Delay 17

3.3.8

System Timing

I/o

Adjustments

4.1

I/O

Restart

H22

KD09

4.1.1

Set

4.1.2

Procedure

4.2

EAE

Restart

E40

KD09

4.2.1

Set

4.2.2

Procedure

4.3

Power Fail 20

4.4

Power

Clear

4.5

PC09

Reader

4.5.1

Set

iii

CONTENTS (Cont)

Page

4.5.2

Procedure 22

ILLUSTRATIONS

Ground Reference 2

Set

100 ns/cm @ 1 V/cm 3

3 Stagger Time 100 ns/cm @ 1 V/cm 4

4 Strobe 100 ns/cm @ 1 V/cm 5

5 Pause Time 100 ns/cm @ 1 V/cm 6

6 Write Time 100 ns/cm @ 1 V/cm 6

7 Core Output and

SAR

50 ns/cm (Sweep

0.5

\-Is/lO)

@ 1 V/cm 7

8 Core Output With Excessive Dispersion 8

9 Core Output With Minimum Dispersion 9

B31

0I Simpl ified Schematic

14(1}

With Correct Timing Adjustment

14(1}

With Incorrect Timing Adjustment

Current Start 20 ns/cm

(0.2

\-IS

1O)

@ 1 V/cm

Start Delay 20 ns/cm @ 1 V/cm

Current 20

nsf

@ 1 V/

Loop

Delay 100 ns/cm @ 1 V/cm

Strobe Start Delay 100 ns/cm @ 1 V/cm

CLR

Position 100 ns/cm @ 1 V/cm

Current Delay 100 ns/cm @ 1 V/cm

I/O

RestartI Incorrect Set

100 ns/cm @ 1 V/cm

I/O

RestartI Correct Set

100 ns/cm @ 1 V/cm

22 Set

for

EAE

Restart 100 ns/cm @ 1 V/cm 20

EAE

Restart 100 ns/cm @ 1 V/cm

Reader Strobe Timing Adjustment 22

25 Reader Strobe Timing AdjustmentI 50% Duty Cycle 23

1. INTRODUCTION

This document

prepared

assist field service personnel

performing a system adjustment

the PDP-9. Procedures

are

given for various adjustments

the Main Memory (MM),

the

Control

Memory (CM), and some

Input/Output

(I/O)

conditions.

The material

organized in a test procedure format and presumes a prior knowledge

the

computer hardware and standard test equipment. It

further assumed that the user

this document

able

prepare and load

certain

diagnostic programs required

the performance of these procedures.

Where necessary, line tracings

osci Iloscope waveforms

are

given to aid the

technician

evaluating

the

system under

test.

These

are

not

idealized

waveforms but

actual

tracings made by

the

manufacturer under factory conditions. Any deviation in these patterns

from

those observed

the

cus-

tomer1s

site

should be

indicative

only

differences

ambient conditions.

MAIN MEMORY

(MM)

2.1

MC70B

Voltage Checks and Adjustments

2.1.1

Main Voltage Check -The

voltage

measured between J01M and HOlM (negative

probe

meter on HOlM). Adjust the potentiometer on the

G804

module, Location (LOC) HJ08 on the

MC70S, for

23.5

Vdc. (See tech tip 108, PDP-9 tech

tip

3 concerning

G622s.)

2.1.2

Second Stage Clamp Voltage Check -The second stage clamp

voltage

measured between

E25B

and

E25N (negative probe of meter on E25B). Adjust the potentiometer on the G008 module,

LOC

E25

the MC70B, for 6 Vdc. (This

the

right-hand potentiometer on

the

G008 as you face the

module

handle.)

2.1.3

Slice Voltage Check -

The

slice

voltage

measured between

E25H

and

E25A

(negative probe

meter

on E25H). Adjust the potentiometer on the G008 module,

LOC

E25

the

MC70B

for

approxi-

mately

4.2

Vdc.

(This

the

left-hand

potentiometer on the G008 as you face

the

module

handle.)

NOTE

This

a ball park figure which will be refined,

after

the memory timing adjustments have been

made, to

balance

the

+lOV margins on

the

sense

amplifiers.

2.2

MC70B Timing Adjustments

2.2.1

Check

the

timing

adjustments

doing

JMP

0 in

LaC

(LaC

00000

600000).

the

computer

will

not

run

this

instruction,

turn

the

DATA

switches

(all

ls)

and

the

ADDRESS switches

DOWN

(all Os). With

the

REPT

(REPEAT)

switch

turned

UP,

turn

the

MAINTEN-

ANCE

switch

DEPOSIT. Use

the

highest

REPT

SPEED

(position

5).

2.2.2

Set

Up -

Set

the

oscilloscope

ALT

MODE

and

set

the

GAIN

both

traces

V/cm.

With

the

input

signals

grounded,

position

the

traces

1.5

above

the

center

line

the

grid.

(The

negative

input

signals

should cross

the

center

line

the

Scope

Grid

(SG)

when

they

are

-1.5V.)

All

times

are

measured

along

the

center

line

the

SG (see

Figure

1).

Figure

Ground

Reference

2.2.3

Procedures -Unless otherwise

noted,

SYNC on probe 1

the

scope.

the

scope

not

equipped for

this,

use

external

sync,

and

then

SYNC on the same signal

is being observed on

probe

less otherwise

noted,

measurements

are

taken

from

the

negative

leading

edge

the

signal on

channell

the

negative

leading

edge

the signal on channel

See

specific

figures for

the

time/cm

settings.

All

locations,

unless otherwise

noted,

refer

the

MC70B

section.

IWARNING I

sure to

GROUND

(GND)

all

probes.

2.2.3.1

Set

Probe 1: F36M = CLOCK

(ClK)

Probe 2: C16D = DIGIT

READ

SYNC

(RS)

Delay

time: 180

Adjust: D35

See

Figure

Figure 2

Set

100 ns/cm @ 1

V/cm

2.2.3.2

Stagger

Delay

2.2.3.3

Probe 1: C16D = DIGIT

Probe 2: H33D =WORD

READ

(WR)

Delay time: Approximately 80

Adjust: D33

See

gure

Strobe

lay

Figure 3

Stagger

Time 100

ns/cm

@ 1

V/cm

Probe 1: C16D =DIGIT

Probe 2:

E32

L =

MEM

Strobe

Delay time:

320

Adjust: E30

See Figure 4

~ThiS

approximate

setting

and

may

refined

later

optimize

memory margins

and

operation.

Any time

that

strobe (E30) is

adjusted

stagger

(D33) must a

Iso

adjusted

the

same amount

maintain

the

correct

relationship

between

core

memory

output

and

strobe (see Figure

7).

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