DNBFC_S12_PCIe H/W Manual Page 3of 20
1Table of Contents
1 Table of Contents.................................................................................................................................. 3
2 Introduction .......................................................................................................................................... 5
2.1 References .................................................................................................................................... 5
2.2 Terminology and Conventions ...................................................................................................... 5
2.3 Things Not To Do........................................................................................................................... 5
2.4 Differences from Revision 1.......................................................................................................... 5
3 Quick Start Guide .................................................................................................................................. 7
1. Setting up your Board ....................................................................................................................... 7
3.1 Power on and configuration ......................................................................................................... 7
3.2 Status LEDs.................................................................................................................................... 7
3.3 Loading the Driver & Running the Board...................................................................................... 8
3.4 Re-Programming the pFPGA over JTAG ........................................................................................ 8
4 On-Board Interfaces............................................................................................................................ 10
4.1 Block diagram.............................................................................................................................. 10
4.2 Chip-to-Chip Bus, “Horizontal” ...................................................................................................10
4.3 Chip-to-Chip Bus, “Vertical”........................................................................................................11
4.4 SF Bus ..........................................................................................................................................11
4.5 DDR3 Discrete Chips ................................................................................................................... 12
4.6 FPGA ID .......................................................................................................................................12
5 Clocking............................................................................................................................................... 13
1. PROC Clock Network ....................................................................................................................... 13
5.1 PFPGASRC Clock Network ........................................................................................................... 13
5.2 MBCLK Clock Network.................................................................................................................13
6 Off-Board Interfaces ........................................................................................................................... 14
6.1 PCI Express Interface................................................................................................................... 14
6.2 Daughter Card Interface ............................................................................................................. 14
6.3 JTAG ports ................................................................................................................................... 15
7 Power and Cooling ..............................................................................................................................17
7.1 Power Connectors.......................................................................................................................17
7.2 Power Sequencing Requirements............................................................................................... 17
