Elan Digital Systems Ltd. 6 HD717 USER’S
GUIDE
2. ABOUT THE HD717
2.1 THE SERIAL COMMS CONTROLLER
The HD717 uses the “industry standard” 85233 Serial Comms
Controller chip (or SCC). This device contains all the logic required
to handle a variety of synchronous and asynchronous serial
protocols. Its operation is not detailed in this document due to its
complexity and the possibility of data book transcription errors.
Instead the reader is strongly advised to obtain the latest User’s
Guide for the generic family of controllers from Zilog Inc. The full
title of the guide is:
“SCC USER’S MANUAL, Zilog Inc, Part No. DC-8293-02”
This is referred to as [REF 1] in this document.
In the UK, Zilog can be reached at (44) (0)1628 39200.
The HD717 maps the SCC directly into the PC’s IO space and so the
device appears just as it would if it were on say an ISA card or PCI
card. The only fundamental difference in the way the SCC operates
on the HD717 is that the data for TX and RX is buffered by 4096 x 8
FIFOs. On an ISA card, it is common to use the SCC in DMA
mode, where two DMA channels are used (one for TX and one for
RX data paths). This is precluded in PCMCIA as only one physical
DMA channel is possible. To overcome this, the HD717 uses
control logic in the card to act like a DMA controller to the SCC.
This means that the SCC must be set to operate in DMA mode even
though the source and destination for the DMA requests never leave
the PC card itself. Instead the data transfers operate transparently (to
the PC) into and out-of the FIFOs. The PC is notified by interrupt
when either the TX FIFO falls below half full or the RX FIFO rises
above half full or the SCC signals a “special condition” e.g. End Of
Message in synchronous modes.
The 4K FIFO buffers effectively shadow normal SCC operations: it
is still possible for the PC to directly read and write the SCC’s own
internal data buffers although doing so must be considered carefully
as accessing the SCC data registers directly may cause missed DMA
