Enclustra Mercury Plus XU9 Manuale utente

Mercury+ XU9 SoC Module

User Manual

Purpose

The purpose of this document is to present the characteristics of Mercury+ XU9 SoC module to the user,

and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU9 SoC

module.

Summary

This document first gives an overview of the Mercury+ XU9 SoC module followed by a detailed description

of its features and configuration options. In addition, references to other useful documents are included.

Product Information Code Name

Product ME-XU9 Mercury+ XU9 SoC Module

Document Information Reference Version Date

Reference / Version / Date D-0000-463-001 04 05.09.2022

Approval Information Name Position Date

Written by DIUN, MMOS Design Engineer 20.05.2019

Verified by MMOS, GKOE Design Expert 24.05.2019

Approved by SJOK Product Manager 05.09.2022

Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland

Phone +41 43 343 39 43 – www.enclustra.com

Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the

prior written permission of Enclustra GmbH, Switzerland.

Although Enclustra GmbH believes that the information included in this publication is correct as of the

date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.

All information in this document is strictly confidential and may only be published by Enclustra GmbH,

Switzerland.

All referenced trademarks are the property of their respective owners.

Document History

Version Date Author Comment

04 05.09.2022 TKAU Updated for revision 2.1 modules: added information on discon-

tinuation of support for power converter switching frequency syn-

chronisation, changes on base board descriptions

03 16.02.2021 DIUN Added information on Mercury heatsinks, added Mercury+ ST1 to

accesories section, added information on FPGA fuses and warranty,

on differential I/Os, on voltage monitoring outputs, removed 15

Gbps limitation on MGTs due to Hirose connector, other style up-

dates

02 15.11.2019 MMOS Added information on revision 1 and 2 modules, other minor cor-

rections

01 03.06.2019 DIUN Version 01, preliminary

D-0000-463-001 2 / 61 Version 04, 05.09.2022

Table of Contents

1 Overview 6

1.1 General................................................... 6

1.1.1 Introduction................................................ 6

1.1.2 Warranty .................................................. 6

1.1.3 RoHS .................................................... 6

1.1.4 DisposalandWEEE............................................ 6

1.1.5 Safety Recommendations and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.6 ElectrostaticDischarge.......................................... 7

1.1.7 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Features .................................................. 7

1.3 Deliverables ................................................ 8

1.4 Accessories................................................. 8

1.4.1 ReferenceDesign............................................. 8

1.4.2 EnclustraBuildEnvironment ...................................... 8

1.4.3 PetalinuxBSP ............................................... 8

1.4.4 EnclustraHeatSink............................................ 9

1.4.5 Mercury+PE1BaseBoard........................................ 9

1.4.6 Mercury+PE3BaseBoard........................................ 9

1.4.7 Mercury+ST1BaseBoard........................................ 9

1.5 XilinxToolSupport ............................................ 10

2 Module Description 11

2.1 BlockDiagram............................................... 11

2.2 Module Configuration and Product Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 EN-NumbersandPartNames...................................... 12

2.4 TopandBottomViews.......................................... 14

2.4.1 TopView .................................................. 14

2.4.2 BottomView................................................ 14

2.5 Top and Bottom Assembly Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.1 TopAssemblyDrawing.......................................... 15

2.5.2 BottomAssemblyDrawing ....................................... 15

2.6 ModuleFootprint............................................. 16

2.7 MechanicalData ............................................. 17

2.8 ModuleConnector ............................................ 17

2.9 UserI/O................................................... 18

2.9.1 Pinout.................................................... 18

2.9.2 I/OPinExceptions ............................................ 19

2.9.3 DifferentialI/Os.............................................. 21

2.9.4 I/OBanks.................................................. 21

2.9.5 VCC_IOUsage............................................... 22

2.9.6 SignalTerminations............................................ 23

2.9.7 MultiplexedI/O(MIO)Pins ....................................... 24

2.9.8 AnalogInputs ............................................... 25

2.10 Multi-Gigabit Transceiver (MGT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.11 Power.................................................... 27

2.11.1 PowerGenerationOverview....................................... 28

2.11.2 PowerEnable/PowerGood ....................................... 29

2.11.3 VoltageSupplyInputs .......................................... 29

2.11.4 VoltageSupplyOutputs ......................................... 30

2.11.5 PowerConsumption ........................................... 30

2.11.6 HeatDissipation.............................................. 30

2.11.7 VoltageMonitoring............................................ 31

2.12 ClockGeneration ............................................. 32

2.13 Reset .................................................... 32

D-0000-463-001 3 / 61 Version 04, 05.09.2022

2.14 LEDs..................................................... 33

2.15 DDR4SDRAM(PS) ............................................ 33

2.15.1 DDR4SDRAMType............................................ 34

2.15.2 SignalDescription ............................................ 34

2.15.3 Termination ................................................ 34

2.15.4 Parameters................................................. 34

2.16 DDR4SDRAM(PL) ............................................ 35

2.16.1 DDR4SDRAMType............................................ 36

2.16.2 SignalDescription ............................................ 36

2.16.3 Termination ................................................ 36

2.16.4 Parameters................................................. 36

2.17 QSPIFlash ................................................. 37

2.17.1 QSPIFlashType.............................................. 37

2.17.2 SignalDescription ............................................ 37

2.17.3 Configuration ............................................... 38

2.17.4 QSPIFlashCorruptionRisk ....................................... 38

2.18 eMMCFlash ................................................ 38

2.18.1 eMMCFlashType............................................. 38

2.18.2 SignalDescription ............................................ 39

2.19 SDCard................................................... 39

2.20 DualGigabitEthernet .......................................... 39

2.20.1 EthernetPHYType ............................................ 39

2.20.2 SignalDescription ............................................ 39

2.20.3 ExternalConnectivity........................................... 40

2.20.4 MDIOAddress............................................... 40

2.20.5 PHYConfiguration ............................................ 40

2.20.6 RGMIIDelaysConfiguration....................................... 41

2.21 USB2.0................................................... 41

2.21.1 USBPHYType............................................... 41

2.21.2 SignalDescription ............................................ 42

2.22 USB3.0................................................... 42

2.23 DisplayPort ................................................ 43

2.24 Real-TimeClock(RTC) .......................................... 43

2.25 SecureEEPROM.............................................. 44

2.25.1 EEPROMType ............................................... 44

3 Device Configuration 45

3.1 ConfigurationSignals .......................................... 45

3.2 ModuleConnectorCDetection .................................... 46

3.3 Pull-UpDuringConfiguration...................................... 46

3.4 Power-onResetDelayOverride .................................... 47

3.5 BootMode................................................. 47

3.6 JTAG..................................................... 48

3.6.1 JTAGonModuleConnector....................................... 48

3.6.2 ExternalConnectivity........................................... 49

3.6.3 JTAGBootMode ............................................. 49

3.7 eMMCBootMode ............................................ 50

3.8 QSPIBootMode ............................................. 50

3.9 SDCardBootMode ........................................... 50

3.10 eMMCFlashProgramming ....................................... 50

3.11 QSPI Flash Programming via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.12 QSPI Flash Programming from an External SPI Master . . . . . . . . . . . . . . . . . . . . . . . 51

3.13 Enclustra Module Configuration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4 I2C Communication 52

4.1 Overview.................................................. 52

D-0000-463-001 4 / 61 Version 04, 05.09.2022

4.2 SignalDescription ............................................ 52

4.3 I2CAddressMap ............................................. 52

4.4 SecureEEPROM.............................................. 53

4.4.1 MemoryMap ............................................... 53

5 Operating Conditions 56

5.1 AbsoluteMaximumRatings....................................... 56

5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6 Ordering and Support 58

6.1 Ordering .................................................. 58

6.2 Support................................................... 58

D-0000-463-001 5 / 61 Version 04, 05.09.2022

1 Overview

1.1 General

1.1.1 Introduction

The Mercury+ XU9 SoC module combines the Xilinx Zynq® UltraScale+ MPSoC (Multiprocessor System-

on-Chip) device with USB 3.0, PCIe® Gen3 ×16, PCIe® Gen2 ×4, two USB 2.0 PHYs, two Gigabit Ethernet

PHYs, DDR4 SDRAM with Error Correction Code (ECC), eMMC flash, multi-gigabit transceivers, high-speed

LVDS I/O, and is available in industrial temperature range, forming a complete and powerful embedded

processing system.

The use of the Mercury+ XU9 SoC module, in contrast to building a custom MPSoC hardware, signif-

icantly reduces development effort and redesign risk and improves time-to-market for the embedded

system.

Together with Mercury+ base boards, the Mercury+ XU9 SoC module allows the user to quickly build a

system prototype and start with application development.

The Enclustra Build Environment [16] is available for the Mercury+ XU9 SoC module. This build system

allows the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose

the desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot

Loader). It downloads and compiles all required software, such as U-Boot, Linux, and BusyBox based root

file system.

1.1.2 Warranty

Please refer to the General Business Conditions, available on the Enclustra website [1].

Warning!

Please note that the warranty of an Enclustra module is voided if the FPGA fuses are blown. This

operation is done at own risk, as it is irreversible. Enclustra cannot test the module in case of a warranty

product return.

1.1.3 RoHS

The Mercury+ XU9 SoC module is designed and produced according to the Restriction of Hazardous

Substances (RoHS) Directive (2011/65/EC).

1.1.4 Disposal and WEEE

The Mercury+ XU9 SoC module must be properly disposed of at the end of its life.

The Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the

Mercury+ XU9 SoC module.

1.1.5 Safety Recommendations and Warnings

Mercury+ modules are not designed to be “ready for operation” for the end-user. These can only be used

in combination with suitable base boards. Proper configuration of the hardware before usage is required.

D-0000-463-001 6 / 61 Version 04, 05.09.2022

Ensure that the power supply is disconnected from the board before inserting or removing the Mercury+

XU9 SoC module, connecting interfaces, or connecting jumpers.

Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage;

over-voltage on power or signal lines can also cause permanent damage to the module.

1.1.6 Electrostatic Discharge

Electronic boards are sensitive to electrostatic discharge (ESD). Please ensure that the product is handled

with care and only in an ESD-protected environment.

1.1.7 Electromagnetic Compatibility

The Mercury+ XU9 SoC module is a Class A product (as defined in IEC 61000-3-2 standard) and is not

intended for use in domestic environments. The product may cause electromagnetic interference, for

which appropriate measures must be taken.

1.2 Features

•Xilinx Zynq® UltraScale+™ MPSoC

•XCZU4CG/XCZU4EV/XCZU5EV/XCZU7EV device

•FBVB900 package

•Dual-/Quad-core ARM® Cortex™-A53 MPCore™ up to 1.333 GHz

•Dual-core ARM® Cortex™-R5 MPCore™ up to 533 MHz

•Mali-400 MP2 GPU (not for CG variants)

•H.264 / H.265 Video Codec (only for EV variants)

•Xilinx 16nm FinFET+ FPGA fabric

•192 user I/Os

•14 ARM peripheral I/Os (SPI, SDIO, CAN, I2C, UART)

•78 FPGA I/Os (single-ended, differential or analog)

•30 HP I/Os

•26 I/Os at 1.2 V (fixed voltage)

•4 I/Os up to 3.3 V (routed via level shifters)

•48 HD I/Os (up to 3.3 V)

•100 MGT signals (clock and data)

•80 GTH MGT signals

•20 GTR MGT signals

•Speedgrade 1 devices: 16 GTH MGTs @ 12.5 Gbit/sec and 8 reference input clock differential pairs

•Other devices: 16 GTH MGTs @ 16.375 Gbit/sec and 8 reference input clock differential pairs

•PCIe Gen3 ×16 (Xilinx built-in PCIe integrated block using GTH lines)

•4 GTR MGTs @ 6 Gbit/sec and 2 reference input clock differential pairs

•PCIe Gen2 ×4 (Xilinx built-in PCIe hard block using GTR lines)

•Up to 4 GB DDR4 SDRAM with ECC on PS side

•Up to 2 GB DDR4 SDRAM on PL side

•64 MB quad SPI flash

•16 GB eMMC flash

•2×Gigabit Ethernet PHY (one PHY shared with one of the USB PHYs)

•2×USB 2.0 PHYs

•PHY0 configured as host or device

•PHY1 configured as host (shared with one of the Gigabit Ethernet PHYs)

•USB 3.0 (Xilinx built-in USB 3.0 hard block using GTR lines)

•Real-time clock

•CAN, UART, SPI, I2C, SDIO/MMC

•5 to 15 V supply voltage

D-0000-463-001 7 / 61 Version 04, 05.09.2022

1.3 Deliverables

•Mercury+ XU9 SoC module

•Mercury+ XU9 SoC module documentation, available via download:

•Mercury+ XU9 SoC Module User Manual (this document)

•Mercury+ XU9 SoC Module Reference Design [2]

•Mercury+ XU9 SoC Module IO Net Length Excel Sheet [3]

•Mercury+ XU9 SoC Module FPGA Pinout Excel Sheet [4]

•Mercury+ XU9 SoC Module User Schematics (PDF) [5]

•Mercury+ XU9 SoC Module Known Issues and Changes [6]

•Mercury+ XU9 SoC Module Footprint (Altium, Eagle, Orcad and PADS) [7]

•Mercury+ XU9 SoC Module 3D Model (PDF) [8]

•Mercury+ XU9 SoC Module STEP 3D Model [9]

•Mercury Mars Module Pin Connection Guidelines [10]

•Mercury Master Pinout [11]

•Mercury Heatsink Application Note [20]

•Enclustra Build Environment [16] (Linux build environment; refer to Section 1.4.2 for details)

•Enclustra Build Environment How-To Guide [17]

•Petalinux BSP and Documentation [18]

1.4 Accessories

1.4.1 Reference Design

The Mercury+ XU9 SoC module reference design features an example configuration for the Zynq Ultra-

Scale+ MPSoC device, together with an example top level HDL file for the user logic.

A number of software applications are available for the reference design, that show how to initialize the

peripheral controllers and how to access the external devices. Pre-compiled binaries are included in the

archive, so that the user can easily check that the hardware is functional.

The reference design can be downloaded from Github: https://github.com/enclustra.

1.4.2 Enclustra Build Environment

The Enclustra Build Environment (EBE) [16] enables the user to quickly set up and run Linux on any En-

clustra SoC module or system board. It allows the user to choose the desired target, and download all

the required binaries, such as bitstream and FSBL. It downloads and compiles all required software, such

as U-Boot, Linux, and BusyBox based root file system.

The Enclustra Build Environment features a graphical user interface (GUI) and a command line interface

(CLI) that facilitates the automatic build flow.

The Enclustra Build Environment How-To Guide [17] describes in more detail how to use the EBE to cus-

tomize the provided software for the user application. The document provides information on the con-

figuration options for U-boot, Linux kernel and Buildroot, debugging possibilities for Linux applications,

customization of device trees and integration of existing or new kernel drivers.

1.4.3 Petalinux BSP

The Enclustra Petalinux BSPs enable the user to quickly set up a Petalinux project and to run Linux on the

Enclustra SoC module or system board.

The documentation [18] describes the build process in detail and allows a user without Petalinux knowl-

edge to build and run the desired design on the target hardware.

D-0000-463-001 8 / 61 Version 04, 05.09.2022

1.4.4 Enclustra Heat Sink

For Mercury modules an Enclustra heat sink is available for purchase along with the product. Please refer

to section 2.11.6 for further information on the available cooling options.

1.4.5 Mercury+ PE1 Base Board

The Mercury+ PE1 is a versatile PCIe® x4 base board equipped with a multitude of I/O interfaces for use

with the Mercury/Mercury+ family of FPGA and SoC modules, providing a head start for building custom

FPGA and SoC based hardware systems.

It is compatible with a multitude of FMC boards from different suppliers to use in data acquisition systems,

motor control, display and camera interfaces, software defined radio and more. The board is equally well

suited for rapid prototyping and for building FPGA systems without designing custom hardware.

For more information visit

https://www.enclustra.com/en/products/base-boards/mercury-pe1-200-300-400/.

Please note that the available features depend on the equipped Mercury module type and on the selected

base board variant.

Warning!

Due to the pinout assignments (pin types and I/O voltage levels) on module connectors B and C,

affecting the FMC interfaces, the compatibility of the Mercury+ XU9 SoC module to the Mercury+ PE1

base board is limited. It is recommended to check the FMC card pinout in detail with the Enclustra

Mercury Master Pinout and with the module and base board schematics.

1.4.6 Mercury+ PE3 Base Board

The Mercury+ PE3 is a versatile PCIe® x8 base board equipped with a multitude of I/O interfaces for use

with the Mercury/Mercury+ family of FPGA and SoC modules, providing a head start for building custom

FPGA and SoC based hardware systems.

This high performance base board provides a versatile set of I/O connectivity options, specialized for

high-speed communication and video applications, including SFP+, QSFP+, HDMI, USB Type-C and Fire-

fly. The board is equally well suited for rapid prototyping and for building FPGA systems without design-

ing custom hardware.

For more information visit https://www.enclustra.com/en/products/base-boards/mercury-pe3/.

Please note that the available features depend on the equipped Mercury module type and on the selected

base board variant.

1.4.7 Mercury+ ST1 Base Board

The Mercury+ ST1 board is a compact, low-cost base board equipped with a multitude of I/O interfaces

for use with the Mercury/Mercury+ family of FPGA and SoC modules.

It provides a versatile set of I/O connectivity options, specialized for video applications, including MIPI,

HDMI and SFP+. The board is equally well suited for rapid prototyping and for building FPGA systems

without designing custom hardware.

For more information visit https://www.enclustra.com/en/products/base-boards/mercury-st1/.

Please note that the available features depend on the equipped Mercury module type and on the selected

base board variant.

D-0000-463-001 9 / 61 Version 04, 05.09.2022

1.5 Xilinx Tool Support

The MPSoC devices equipped on the Mercury+ XU9 SoC module are supported by the Vivado HL Web-

PACK Edition software, which is available free of charge. Please contact Xilinx for further information.

D-0000-463-001 10 / 61 Version 04, 05.09.2022

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