Index DW9937S Manuale utente

SERVICE MANUAL

DW9937S

Ver 0.0

INDEX

PREFACE

FEATURES

........................................................................................................................

FRONT PANEL&REAR PANEL

........................................................................................................................

REMOTE CONTROL ................................................................................................................. 3

SCHEMA

PARTSLIST

TIC DIAGRAM&PCB SILKSCREEN

MAIN BOARD SCHEMATIC AND PCB LAYOUT

............................................................................

74-84

AV BOARD SCHEMATIC ..................................................................................................... 85-95

KEY BOARD SCHEMATIC .......................................................................................................

POWER BOARD SCHEMATIC ........................................................................................... 97

PARTS SPECIFICATIONS

SST39VF16 0............................................................................................................................... 6

M13S128168A ............................................................................................................................

..................................................................................................................................

TSB41AB1 8

TVP5146

...................................................................................................................... 9

CS4360

........................................................................................................................................ 13

CS5333 ......................................................................................................................................... 15

74HC/HCT14 ............................................................................................................................. 17

74ALVT16373 ...................................................................................................................... 18

MM1313 ............................................................................................................................................ 19-30

MAX4051 .......................................................................................................................................... 31-50

FSDM07652RB ................................................................................................................................ 51-70

LP2995

................................................................................................................

PQXXXEZ02Z .......................................................................................................................... 72

TUNER .............................................................................................................. 73

MAIN PANEL BOARDKEY

......................................................................................................................

103-104

POWER BOARD .............................................................................................................. 105-107

...................................................................................................................... 5

EXPLODED VIEW

BLOCK DIAGRAM

.............................................................................................................

BLOCK DIAGRAM

VCR MODLE 98-100

AV BOARD 108-110

MAIN BOARD .............................................................................................................................. 101-102

....................................................................................................................................

.........................................................................................................................

BLOCK DIAGRAM

CVBS &mixed Audio inputs Video inputs Audio outputs Video outputs

audio Signals outputs (except mixed L/R Audio) (except CVBS )

DVD CVBS signal

DVD L&R audio signals AV board

VCR L&R audio signals

Main board

VCR CVBS signal

wake up signal

Power on/off signal

Control signal(s)

Power board Video signal(s) Main pannel board

Audio signal(s)

DNM8602

VCR HC4052

5146

Video ADC

CS5333

Audio ADC

CS4360

Audio

key matrix

µPD16316

MSP3415

CD4052

VMM1313

AV Channel

Switch

VFD-DISP

POWER SUPPLY

EXPLODED VIEW

16 Megabit Multi-Purpose Flash

SST39VF160Q / SST39VF160

Advance Information

FIGURE 1: PIN ASSIGNMENTS FOR 48-PIN TSOP PACKAGES

FUNCTIONAL BLOCK DIAGRAM

FIGURE 2: PIN ASSIGNMENTS FOR 48-PIN TFBGA

Y-Decoder

I/O Buffers and Data Latches

329 ILL B1.2

Address Buffer & Latches

X-Decoder

DQ15 - DQ0

A19 - A0

OE#

CE#

WE#

16,777,216 bit

EEPROM

Cell Array

Control Logic

VDDQ

A15

A14

A13

A12

A11

A10

A19

WE#

A18

A17

A16

VDDQ

VSS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VDD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

329 ILL F01.2

Standard Pinout

Top View

Die Up

SST39VF160Q

A15

A14

A13

A12

A11

A10

A19

WE#

A18

A17

A16

VSS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VDD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

329 ILL F01a.0

Standard Pinout

Top View

Die Up

SST39VF160

329 ILL F02.4

SST39VF160Q

123456

A3 A7 NC WE# A9 A13

A4 A17 NC NC A8 A12

A2 A6 A18 NC A10 A14

A1 A5 NC A19 A11 A15

A0 DQ0 DQ2 DQ5 DQ7 A16

CE# DQ8 DQ10 DQ12 DQ14 VDDQ

OE# DQ9 DQ11 VDD DQ13 DQ15

VSS DQ1 DQ3 DQ4 DQ6 VSS

329 ILL F02a.0

SST39VF160

123456

A3 A7 NC WE# A9 A13

A4 A17 NC NC A8 A12

A2 A6 A18 NC A10 A14

A1 A5 NC A19 A11 A15

A0 DQ0 DQ2 DQ5 DQ7 A16

CE# DQ8 DQ10 DQ12 DQ14 NC

OE# DQ9 DQ11 VDD DQ13 DQ15

VSS DQ1 DQ3 DQ4 DQ6 VSS

ESMT

 



M13S128168A

Elite Semiconductor Memory TechnologyInc.

Publication Date:Nov.2002

Revision :0.2 





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

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  

45-45 2

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

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



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

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











66 PIN TSOP(II)

(400mil x 875mil)

(0.65 mm PIN PITCH)



 



 

 

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

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

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 

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

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

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

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

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

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



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



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





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 

Revision :0.2 



   



SLLS423D –JUNE 2000 –REVISED SEPTEMBER 2002

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

description (continued)

required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is

in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it

to normal operation.

When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a

low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the

TSB41AB1 disables its internal clock generators and also disables various voltage and current reference

circuits depending on the state of the port (some reference circuitry must remain active in order to detect new

cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the

ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt

enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a

port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to notify

the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected

on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes

active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high

when the TSB41AB1 is in the low-power mode.

The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the

C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when

the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is

inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet

addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output

when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON

output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON

to be active.

PHP package terminal diagram

14 15

AGND

AVDD

AGND

TPBIAS

TPA+

TPA–

TPB+

TPB–

AGND

AVDD

SYSCLK

CTL0

CTL1

17 18 19 20

47 46 45 44 4348 42 40 39 3841

21 22 23 24

PHP PACKAGE

(TOP VIEW)

TSB41AB1

PLLGND

PLLV

FILTER1

FILTER0

LREQ

DGND

TESTM

C/LKON

PC1

PC2

ISO

CPS

RESET

DGND

LPS

PC0 DD

DVDD

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