Intel PXA255 Manuale utente

Intel® PXA255 Processor

Electrical, Mechanical, and Thermal Specification

Data Sheet

Product Features

■High Performance Processor

— Intel® XScale™ Microarchitecture

—32 KB Instruction Cache

—32 KB Data Cache

—2 KB “mini” Data Cache

—Extensive Data Buffering

■Intel® Media Processing Technology

—Enhanced 16-bit Multiply

—40-bit Accumulator

■Flexible Clocking

—CPU clock from 100 to 400 MHz

—Flexible memory clock ratios

—Frequency change modes

■Rich Serial Peripheral Set

—AC97 Audio Port

—I2S Audio Port

—USB Client Controller

—High Speed UART

—Second UART with flow control

—UART with hardware flow control

—FIR and SIR infrared comm ports

■Low Power

—Less than 500 mW Typical Internal

Dissipation

—Supply Voltage may be Reduced to

1.00 V

—Low Power/Sleep Modes

■High Performance Memory Controller

—Four Banks of SDRAM - up to 100 MHz

—Five Static Chip Selects

—Support for PCMCIA or Compact Flash

—Companion Chip interface

■Additional Peripherals for system

connectivity

—Multimedia Card Controller (MMC)

—SSP Controller

—Network SSP controller for baseband

—I2C Controller

—Two Pulse Width Modulators (PWMs)

—All peripheral pins double as GPIOs

■Hardware debug features

■Hardware Performance Monitoring features

Order Number: 278805-002

February, 2004

2Data Sheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The PXA255 processor EMTS Data Sheet may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled

platforms may require licenses from various entities, including Intel Corporation.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

*Other names and brands may be claimed as the property of others.

PXA255 Processor — Electrical, Mechanical, and Thermal Specification

Data Sheet 3

Contents

1.0 About This Document............................................................................................7

2.0 Functional Overview ..............................................................................................7

3.0 Package Information ..............................................................................................8

3.1 Package Introduction.....................................................................................8

3.1.1 Functional Signal Definitions ............................................................8

3.1.1.1 PXA255 Processor Signal Pin Descriptions .....................8

3.2 Package Power Ratings ..............................................................................22

4.0 Electrical Specifications ......................................................................................22

4.1 Absolute Maximum Ratings.........................................................................22

4.2 Power Consumption Specifications.............................................................23

4.3 Operating Conditions...................................................................................25

4.4 Targeted DC Specifications.........................................................................26

4.5 Targeted AC Specifications.........................................................................27

4.6 Oscillator Electrical Specifications...............................................................28

4.6.1 32.768-kHz Oscillator Specifications..............................................28

4.6.2 3.6864 MHz Oscillator Specifications.............................................29

4.7 Reset and Power AC Timing Specifications................................................30

4.7.1 Power-On Timing ...........................................................................30

4.7.2 Hardware Reset Timing..................................................................32

4.7.3 Watchdog Reset Timing .................................................................32

4.7.4 GPIO Reset Timing ........................................................................32

4.7.5 Sleep Mode Timing ........................................................................33

4.8 Memory Bus and PCMCIA AC Specifications .............................................35

4.9 Peripheral Module AC Specifications ..........................................................37

4.9.1 LCD Module AC Timing..................................................................37

4.9.2 SSP Module AC Timing..................................................................37

4.9.3 Boundary Scan Test Signal Timings ..............................................38

4.10 AC Test Conditions .....................................................................................39

PXA255 Processor — Electrical, Mechanical, and Thermal Specification

4Data Sheet

Figures

1 Processor Block Diagram...................................................................................... 8

2 PXA255 processor .............................................................................................. 19

3 Power-On Reset Timing ...................................................................................... 31

4 Hardware Reset Timing ...................................................................................... 32

5 GPIO Reset Timing ............................................................................................. 33

6 Sleep Mode Timing ............................................................................................. 34

7 LCD AC Timing Definitions ................................................................................. 37

8 SSP AC Timing Definitions ................................................................................. 38

9 AC Test Load ...................................................................................................... 39

Tables

1 Related Documentation......................................................................................... 7

2 Processor Pin Types ............................................................................................. 9

3 Pin and Signal Descriptions for the PXA255 Processor........................................ 9

4 Pin Description Notes.......................................................................................... 18

5 PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order ....20

6θJA and Maximum Power Ratings........................................................................ 22

7 Absolute Maximum Ratings ................................................................................ 23

8 Power Consumption Specifications for PXA255 processor ................................24

9 Voltage, Temperature, and Frequency Electrical Specifications......................... 25

10 Standard Input, Output, and I/O Pin DC Operating Conditions........................... 26

11 Standard Input, Output, I/O Pin DC Operating Conditions for 2.5-V Memory ..... 27

12 Standard Input, Output, and I/O Pin AC Operating Conditions ........................... 28

13 32.768-kHz Oscillator Specifications................................................................... 28

14 3.6864-MHz Oscillator Specifications ................................................................. 29

15 Power-On Timing Specifications ......................................................................... 31

16 Hardware Reset Timing Specifications ............................................................... 32

17 GPIO Reset Timing Specifications...................................................................... 33

18 Sleep Mode Timing Specifications ...................................................................... 34

19 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications.................... 35

20 Variable Latency I/O Interface AC Specifications ............................................... 35

21 Card Interface (PCMCIA or Compact Flash) AC Specifications ......................... 36

22 Synchronous Memory Interface AC Specifications 1 ..........................................36

23 LCD AC Timing Specifications ............................................................................ 37

24 SSP AC Timing Specifications ............................................................................ 38

25 Boundary Scan Test Signal Timing..................................................................... 38

PXA255 Processor — Electrical, Mechanical, and Thermal Specification

Data Sheet 5

Revision History

Date Revision Description

March 2003 -001 First public release of the EMTS

February 2004 -002 Updated 400 MHz Idle mode power.

PXA255 Processor — Electrical, Mechanical, and Thermal Specification

6Data Sheet

About This Document

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification 7

1.0 About This Document

This is the electrical, mechanical, and thermal specification data sheet for the Intel® PXA255

Processor. This data sheet contains a functional overview, mechanical data, package signal

locations, targeted electrical specifications (simulated), and bus functional waveforms. Detailed

functional descriptions other than parametric performance is published in the Intel® PXA255

Processor Developer's Manual. Refer to Table 1, “Related Documentation” for a list of documents

that support the PXA255 processor.

2.0 Functional Overview

The PXA255 processor provides high integration, high performance and low power consumption

for portable handheld and handset devices. These processors incorporate the Intel® XScale™

Microarchitecture based on the ARM* V5TE architecture. Refer to the Intel® XScale™

Microarchitecture for the Intel® PXA250 and PXA210 Applications Processors User’s Manual for

implementation details, extensions, and options implemented by the XScale microarchitecture.

The processor memory interface supports a variety of memory types that allow flexible design

requirements. Hooks for connection to two companion chips permit glueless connection to external

devices. An integrated LCD display controller supports displays and permits 1, 2, and 4-bit

grayscale, and 8- or 16-bit color pixels. A 256-byte palette RAM provides flexible color mapping

capabilities.

A rich set of serial devices as well as general-system resources provide enough compute and

connectivity capability for many applications. For details on the programming model and theory of

operation of each of these units, refer to the Intel® PXA255 Processor Developer's Manual. For the

processor block diagram, refer to Figure 1, “Processor Block Diagram” on page 8.

Table 1. Related Documentation

Document Title Order / Contact

Intel® PXA255 Processor Developer's Manual 278693

Intel® XScaleTM Microarchitecture for the PXA250 and PXA210 Applications

Processors Developer's Manual 278525

Intel® PXA255 Processor Design Guide 278694

Package Information

8Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

3.0 Package Information

3.1 Package Introduction

The PXA255 processor is offered in a 256-pin mBGA (refer to Figure 2, “PXA255 processor” on

page 19).

3.1.1 Functional Signal Definitions

3.1.1.1 PXA255 Processor Signal Pin Descriptions

Table 3, “Pin and Signal Descriptions for the PXA255 Processor” on page 9 describes the signal

definitions for the PXA255 processor. Figure 2, “PXA255 processor” on page 19 illustrates the

physical characteristics of the PXA255 processor. Table 5, “PXA255 processor 256-Lead

17x17mm mBGA Pinout — Ballpad No. Order” on page 20 describes the pinout for the PXA255

processor.

Figure 1. Processor Block Diagram

Intelﬁ XScale

Microarchitecture

Color or

Grayscale

LCD

Controller

RTC

OS Timer

PWM(2)

Int.

Controller

Clocks &

Power Man.

I2S

AC97

UARTs

NSSP

Slow IrDA

SSP

USB

Client

General Purpose I/O

ASIC

Socket

3.6864

MHz

Osc

32.768

KHz

Osc

DMA Controller

and Bridge

XCVR

SDRAM/

SMROM

4 banks

ROM/

Flash/

SRAM

4 banks

I2C

Fast IrDA

MMC

Peripheral Bus

System Bus

Memory

Controller

Variable

Latency I/O

Control

PCMCIA

& CF

Control

Dynamic

Memory

Control

Static

Memory

Control

Package Information

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification 9

Some of the processor pins can be connected to multiple signals. The GAFRn_m registers

determine the signal connected to the pin. Some signals can go to multiple pins. The signal must be

routed to one pin only by using the GAFRn_m registers. Because this is true, some pins are listed

twice—once in each unit that can use the pin. Not all peripherals can be used simutaneously in one

design because different peripherals share the same pins.

Table 2. Processor Pin Types

Type Function

IC CMOS input

OC CMOS output

OCZ CMOS output, Hi-Z

ICOCZ CMOS bidirectional, Hi-Z

IA Analog Input

OA Analog output

IAOA Analog bidirectional

SUP Supply pin (either VCC or VSS)

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)

Pin Name Type Signal Descriptions Reset State Sleep State

Memory Controller Pins

MA[25:0] OCZ Memory address bus. (output) Signals the address

requested for memory accesses. Driven Low Driven Low

MD[15:0] ICOCZ Memory data bus. (input/output) Lower 16 bits of the

data bus. Hi-Z Driven Low

MD[31:16] ICOCZ Memory data bus. (input/output) Used for 32-bit

memories. Hi-Z Driven Low

nOE OCZ Memory output enable. (output) Connect to the output

enables of memory devices to control data bus drivers. Driven High Note [4]

nWE OCZ Memory write enable. (output) Connect to the write

enables of memory devices. Driven High Note [4]

nSDCS[3:0] OCZ

SDRAM CS for banks 3 through 0. (output) Connect to

the chip select (CS) pins for SDRAM. For the PXA255

processor processor nSDCS0 can be Hi-Z, nSDCS1-3

cannot.

Driven High Note [5]

DQM[3:0] OCZ

SDRAM DQM for data bytes 3 through 0. (output)

Connect to the data output mask enables (DQM) for

SDRAM.

Driven Low Driven Low

nSDRAS OCZ SDRAM RAS. (output) Connect to the row address

strobe (RAS) pins for all banks of SDRAM. Driven High Driven High

nSDCAS OCZ SDRAM CAS. (output) Connect to the column address

strobe (CAS) pins for all banks of SDRAM. Driven High Driven High

SDCKE[0] OC

Synchronous Static Memory clock enable. (output)

Connect to the CKE pins of SMROM. The memory

controller provides control register bits for de-assertion.

Driven Low Driven Low

Package Information

10 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

SDCKE[1] OC

SDRAM and/or Synchronous Static Memory clock

enable. (output) Connect to the clock enable pins of

SDRAM. It is deasserted during sleep. SDCKE[1] is

always de-asserted upon reset. The memory controller

provides control register bits for de-assertion.

Driven low Driven low

SDCLK[0] OC

Synchronous Static Memory clock. (output) Connect to

the clock (CLK) pins of SMROM. It is driven by either the

internal memory controller clock, or the internal memory

controller clock divided by 2. At reset, all clock pins are

free running at the divide-by-2 clock speed and may be

turned off via free-running control register bits in the

memory controller. The memory controller also provides

control register bits for clock division and deassertion of

each SDCLK pin. SDCLK[0] control register assertion bit

defaults to on if the boot-time static memory bank 0 is

configured for SMROM.

SDCLK[1] OCZ SDRAM Clocks (output) Connect SDCLK[1] and

SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1

and 2/3, respectively. They are driven by either the

internal memory controller clock, or the internal memory

controller clock divided by 2. At reset, all clock pins are

free running at the divide-by-2 clock speed and may be

turned off via free-running control register bits in the

memory controller. The memory controller also provides

control register bits for clock division and de-assertion of

each SDCLK pin. SDCLK[2:1] control register assertion

bits are always de-asserted upon reset.

Driven Low Driven Low

SDCLK[2] OC Driven Low Driven Low

nCS[5]/

GPIO[33] ICOCZ

Static chip selects. (output) Chip selects to static

memory devices such as ROM and Flash. Individually

programmable in the memory configuration registers.

nCS[5:0] can be used with variable latency I/O devices.

Pulled High -

Note[1] Note [4]

nCS[4]/

GPIO[80] ICOCZ

nCS[3]/

GPIO[79] ICOCZ

nCS[2]/

GPIO[78] ICOCZ

nCS[1]/

GPIO[15] ICOCZ

nCS[0] ICOCZ Static chip select 0. (output) Chip select for the boot

memory. nCS[0] is a dedicated pin. Driven High Note [4]

RD/nWR OCZ Read/Write for static interface. (output) Signals that the

current transaction is a read or write. Driven Low Holds last state

RDY/

GPIO[18] ICOCZ

Variable latency I/O ready pin. (input) Notifies the

memory controller when an external bus device is ready

to transfer data.

Pulled High -

Note[1] Note [3]

L_DD[8]/

GPIO[66] ICOCZ

LCD display data. (output) Transfers pixel information

from the LCD controller to the external LCD panel.

Memory controller alternate bus master request.

(input) Allows an external device to request the system

bus from the memory controller.

Pulled High -

Note[1] Note [3]

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)

Pin Name Type Signal Descriptions Reset State Sleep State

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