ISSI IS31AP2121 Manuale utente

IS31AP2121

Integrated Silicon Solution, Inc. – www.issi.com 1

Rev. C, 10/20/2015

2×25W STEREO / 1×50W MONO DIGITAL AUDIO AMPLIFIER

WITH 20 BANDS EQ FUNCTIONS, DRC AND 2.1CH MODE October 2015

GENERAL DESCRIPTION

The IS31AP2121 is a digital audio amplifier capable of

driving 25W (BTL) each to a pair of 8Ωspeakers and

50W (PBTL) to a 4Ωspeaker operating at 24V supply

without external heat-sink or fan. The IS31AP2121 is

also capable of driving 4Ω, 12W (SE)×2 + 8Ω, 25W

(BTL)×1 at 24V supply for 2.1CH application.

The IS31AP2121 can provide advanced audio

processing functions, such as volume control, 20 EQ

bands, audio mixing, 3D surround sound and Dynamic

Range Control (DRC). These are fully programmable

via a simple I2C control interface. Robust protection

circuits are provided to protect the IS31AP2121 from

damage due to accidental erroneous operating

condition. The full digital circuit design of IS31AP2121

is more tolerant to noise and PVT (Process, Voltage,

and Temperature) variation than the analog Class-AB

or Class-D audio amplifier counterpart implemented by

analog circuit design. IS31AP2121 is pop free during

instantaneous power on/off or mute/shut down

switching because of its robust built-in anti-pop circuit.

APPLICATIONS

TV audio

Boom-box, CD and DVD receiver, docking system

Powered speaker

Wireless audio

FEATURES

16/18/20/24-bits input with I2S, Left-alignment and

Right-alignment data format

PSNR & DR (A-weighting)

Loudspeaker: 104dB (PSNR), 110dB (DR) @24V

Multiple sampling frequencies (FS)

- 32kHz / 44.1kHz / 48kHz and

- 64kHz / 88.2kHz / 96kHz and

- 128kHz / 176.4kHz / 192kHz

System clock = 64x, 128x, 192x, 256x, 384x,

512x, 576x, 768x, 1024x Fs

- 64x~1024x FSfor 32kHz / 44.1kHz / 48kHz

- 64x~512x FSfor 64kHz / 88.2kHz / 96kHz

- 64x~256x FSfor 128kHz / 176.4kHz / 192kHz

Supply voltage

- 3.3V for digital circuit

- 10V~26V for speaker driver

Supports 2.0CH/2.1CH/Mono configuration

Loudspeaker output power for at 24V

- 10W ×2CH into 8Ω@0.16% THD+N for stereo

- 15W ×2CH into 8Ω@0.19% THD+N for stereo

- 25W ×2CH into 8Ω@0.3% THD+N for stereo

Sound processing including:

- 20 bands parametric speaker EQ

- Volume control (+24dB ~ -103dB, 0.125dB/step),

- Dynamic range control (DRC)

- Dual band dynamic range control

- Power clipping

- 3D surround sound

- Channel mixing

- Noise gate with hysteresis window

- Bass/Treble tone control

- Bass management crossover filter

- DC-blocking high-pass filter

Anti-pop design

Short circuit and over-temperature protection

Supports I2C control without MCLK

I2C control interface with selectable device

address

Support BCLK system

Support hardware and software reset

Internal PLL

LV Under-voltage shutdown and HV Under-voltage

detection

Power saving mode

IS31AP2121

Integrated Silicon Solution, Inc. – www.issi.com 2

Rev. C, 10/20/2015

TYPICAL APPLICATION CIRCUIT

Figure 1 Typical Application Circuit (For Stereo)

BEAD

470pF

BEAD

470pF

OUTLA

OUTLB

OUTRA

OUTRB

DVDD

OUTLA

SDA

IS31AP2121

0.1 F

4.7k

VDD

OUTRB

DGND

SCL

4.7k

VDD

RSTB

PDB

1M1M

Micro

Controller

1 F 1 F

ERRORB

MCLK

BCLK

LRCIN

SDATA

VCCLA

VCCLB

GNDL

VCC

0.1 F470 F

VCCRA

VCCRB

GNDR

VCC

0.1 F 0.1 F

0.1 F

OUTRA

OUTLB

PBTL

1nF

Speaker

15 H

BEAD

470pF

BEAD

470pF

15 H

220nF

100nF

*Note 4

*Note 2

22 36

3,44

34,41

13,27

9,28

Digital

Audio

Source

470 F

Figure 2 Typical Application Circuit (For Mono)

Pin Logic 0 1

PDB Power Down Normal

RSTB Reset Normal

PBTL Stereo Mono

IS31AP2121

Integrated Silicon Solution, Inc. – www.issi.com 3

Rev. C, 10/20/2015

Figure 3 Typical Application Circuit (For 2.1CH) (Note 5)

Pin Logic 0 1

PDB Power Down Normal

RSTB Reset Normal

PBTL X X

Note 1: When concerning about short-circuit protection or performance, it is suggested using the choke with its IDC larger than 7A.

Note 2: These capacitors should be placed as close to speaker jack as possible, and their values should be determined according to EMI test

results.

Note 3: The snubber circuit can be removed while the VCC ≤20V.

Note 4: When concerning about short-circuit protection or performance, it is suggested using the choke with its IDC larger than 14A.

Note 5: 2.1CH configuration, it programs by I2C via register address 0x11, D4 bit SEM.

IS31AP2121

Integrated Silicon Solution, Inc. – www.issi.com 4

Rev. C, 10/20/2015

PIN CONFIGURATION

Package Pin Configuration (Top View)

eLQFP-48

VCCLA

OUTLA

VCCLB

PBTL

DGND

DVDD

PDB

BCLK

SDATA

OUTLB

GNDL

CLK_OUT

SCL

LRCIN

DVDD

SDA

ERRORB

DGND

RSTB

OUTRA

VCCLB

VCCRB

GNDR

MCLK

VCCRB

VCCRA

OUTRB36

IS31AP2121

Integrated Silicon Solution, Inc. – www.issi.com 5

Rev. C, 10/20/2015

PIN DESCRIPTION

No. Pin Description Characteristics

1 OUTLA Left channel output A.

2 VCCLA Left channel supply A.

3,44 VCCLB Left channel supply B.

4~6,10~12 NC Not connected.

7 CLK_OUT

PLL ratio setting pin during power up, this pin

is monitored on the rising edge of reset. PMF

ratio.

Low: PMF [3:0]=[0000], 1 time of PLL ratio to

avoid system MCLK over flow. High: PMF

[3:0]=[0100], 4 times of PLL ratio.

This pin could be clock output pin also during

normal operating if EN_CLK_OUT register bit

is enabled.

TTL output buffer, internal pull low with

an 80kΩresistor.

8 PBTL

Stereo/mono configuration pin (Low: Stereo;

High: Mono).

9,28 DGND Digital ground.

13,27 DVDD Digital power.

14 ERRORB

ERRORB pin is a dual function pin. One is

I2C address setting during power up. The

other one is error status report (low active). It

sets by register of A_SEL_FAULT at address

0x13 D6 to enable it.

This pin is monitored on the rising edge

of reset. A value of Low (15kΩpull

down) sets the I2C device address to

0x30 and a value of High (15kΩpull up)

sets it to 0x31.

15 MCLK Master clock input. Schmitt trigger TTL input buffer, internal

pull Low with an 80kΩresistor.

16~18,26 NC Not connected.

19 PDB Power down, low active. Schmitt trigger TTL input buffer, internal

pull High with a 330kΩresistor.

20 LRCIN Left/Right clock input (FS). Schmitt trigger TTL input buffer, internal

pull Low with an 80kΩresistor.

21 BCLK Bit clock input (64FS). Schmitt trigger TTL input buffer, internal

pull Low with an 80kΩresistor.

22 SDATA I2S serial audio data input. Schmitt trigger TTL input buffer

23 SDA I2C serial data. Schmitt trigger TTL input buffer

24 SCL I2C serial clock input. Schmitt trigger TTL input buffer

25 RSTB Reset, low active. Schmitt trigger TTL input buffer, internal

pull High with a 330kΩresistor.

29~33,40 NC Not connected.

IS31AP2121

Integrated Silicon Solution, Inc. – www.issi.com 6

Rev. C, 10/20/2015

PIN DESCRIPTION (CONTINUE)

No. Pin Description Characteristics

34,41 VCCRB Right channel supply B.

35 VCCRA Right channel supply A.

36 OUTRB Right channel output B.

37,38 GNDR Right channel ground.

39 OUTRA Right channel output A.

42,43,45 NC Not connected.

46 OUTLB Left channel output B.

47,48 GNDL Left channel ground.

Thermal Pad Connect to DGND.

IS31AP2121

Integrated Silicon Solution, Inc. – www.issi.com 7

Rev. C, 10/20/2015

ORDERING INFORMATION

Industrial Range: 0°C to +70°C

Order Part No. Package QTY

IS31AP2121-LQLS1 e-LQFP-48, Lead-free 250/Tray

Copyright©2015IntegratedSiliconSolution,Inc.Allrightsreserved.ISSI reservestherighttomakechangestothisspecificationanditsproductsatany

timewithoutnotice.ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.Customersare

advisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts.

IntegratedSiliconSolution,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionofthe

productcanreasonablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.Productsarenot

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a.)theriskofinjuryordamagehasbeenminimized;

b.)theuserassumeallsuchrisks;and

c.)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances

IS31AP2121

Integrated Silicon Solution, Inc. – www.issi.com 8

Rev. C, 10/20/2015

ABSOLUTE MAXIMUM RATINGS

Supply for driver stage (VCCR, VCCL), VCC -0.3V ~ +30V

Supply for digital circuit (DVDD), VDD -0.3V ~ +3.6V

Input voltage (SDA,SCL,RSTB,PDB,ERRORB,MCLK,

BCLK,LRCIN,SDATA,PBTL), VIN -0.3V ~ +3.6V

Thermal resistance, θJA 27.4°C/W

Junction temperature range, TJ 0°C ~ 150°C

Storage temperature range, TSTG -65°C ~ +150°C

ESD (HBM)

ESD (CDM)

±2kV

±500V

Note:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is

not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Condition Min. Typ. Max. Unit

VCC Supply for driver stage to VCCR/L 10 26 V

VDD Supply for digital circuit 3.15 3.45 V

TJJunction operating temperature 0 125 °C

TAAmbient operating temperature 0 70 °C

DC ELECTRICAL CHARACTERISTICS

TA=25°C, unless otherwise noted.

Symbol Parameter Condition Min. Typ. Max. Unit

IPDH VCC supply current during power down VCC = 24V 10 200 µA

IPDL DVDD supply current during power

down VDD = 3.3V, PBTL=Low 13 20 µA

ICCH Quiescent current for VCC (50%/50%

PWM duty) VCC = 24V 37 mA

ICCL Quiescent current for DVDD (Un-mute) VDD = 3.3V, PBTL=Low 70 mA

VUVH Under-voltage disabled (For DVDD) 2.8 V

VUVL Under-voltage enabled (For DVDD) 2.7 V

RDS(ON)

Static drain-to-source on-state resistor,

PMOS VCC =24V, ID= 500mA

260

mΩ

Static drain-to-source on-state resistor,

NMOS 230

ISC L/R channel over-current protection VCC =24V, ID=500mA

(Note 1)

7 A

Mono channel over-current protection 14

Junction temperature for driver

shutdown 158 °C

Temperature hysteresis for recovery

from shutdown 33 °C

IS31AP2121

Integrated Silicon Solution, Inc. – www.issi.com 9

Rev. C, 10/20/2015

DC ELECTRICAL CHARACTERISTICS (CONTINUE)

TA=25°C, unless otherwise noted.

Symbol Parameter Condition Min. Typ. Max. Unit

Logic Electrical Characteristics

VIH High level input voltage VDD =3.3V 2.0 V

VIL Low level input voltage VDD =3.3V 0.8 V

VOH High level output voltage VDD =3.3V 2.4 V

VOL Low level output voltage VDD =3.3V 0.4 V

CIN Input capacitance 6.4 pF

Note 1: Loudspeaker over-current protection is only effective when loudspeaker drivers are properly connected with external LC filters. Please

refer to the application circuit example for recommended LC filter configuration.

AC ELECTRICAL CHARACTERISTICS

TA=25°C, VCC=24V, VDD = 3.3V, fS= 48kHz, RL=8Ωwith passive LC lowpass filter (L= 15µH, RDC= 63mΩ,

C=220nF), input is 1kHz sinewave, volume is 0dB unless otherwise specified.

Symbol Parameter Condition Min. Typ. Max. Unit

PORMS output power (Note 2)

THD+N=0.16%, VCC=24V, +8dB

volume 10

THD+N=0.25%, VCC=24V, +8dB

volume 20

THD+N=1%, VCC=12V, +8dB volume 7.5

THD+N=10%, VCC=12V, +8dB volume 9

PBTL Mode, VCC=24V, RL=4Ω,

THD+N=0.16%, +8dB volume 40

PBTL Mode, VCC=12V, RL=4Ω,

THD+N=1%, +8dB volume 15

PBTL Mode, VCC=12V, RL=4Ω,

THD+N=10%, +8dB volume 18

2.1CH Mode, VCC=24V, RL=4Ω,

THD+N=0.14%, +8dB volume 5

2.1CH Mode, VCC=24V, RL=4Ω,

THD+N=0.16%, +8dB volume 10

2.1CH Mode, VCC=12V, RL=4Ω,

THD+N=1%, +8dB volume 3.7

2.1CH Mode, VCC=12V, RL=4Ω,

THD+N=10%, +8dB volume 4.5

THD+N Total harmonic distortion +

noise

VCC=24V, PO = 7.5W 0.15 %

VCC=12V, Po = 2.5W 0.16

VNO Output noise 20Hz ~ 20kHz (Note 3) 120 µV

SNR Signal-to-noise ratio +8dB volume, input level is -9dB

(Note 3) 104 dB

DR Dynamic range +8dB volume, input level is -68dB

(Note 3) 110 dB

PSRR Power supply ripple rejection VRIPPLE = 1VRMS at 1kHz -71 dB

Channel separation 1W @1kHz -81 dB

IS31AP2121

Integrated Silicon Solution, Inc. – www.issi.com 10

Rev. C, 10/20/2015

I2C DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 4)

Symbol Parameter Standard Mode Fast Mode Unit

Min. Max. Min. Max.

fSCL Serial-Clock frequency 0 100 0 400 kHz

tBUF Bus free time between a STOP and a START

condition 4.7 1.3 μs

tHD, STA Hold time (repeated) START condition 4.0 0.6 μs

tSU, STA Repeated START condition setup time 4.7 0.6 μs

tSU, STO STOP condition setup time 4.0 0.6 μs

tHD, DAT Data hold time 0 3.45 0 0.9 μs

tSU, DAT Data setup time 250 100 ns

tLOW SCL clock low period 4.7 1.3 μs

tHIGH SCL clock high period 4.0 0.6 μs

tRRise time of both SDA and SCL signals,

receiving 1000 20+0.1Cb300 ns

tFFall time of both SDA and SCL signals,

receiving 300 20+0.1Cb300 ns

CbCapacitive load for each bus line 400 400 pF

VNL Noise margin at the low level for each

connected device (including hysteresis) 0.1VDD 0.1VDD V

VNH Noise margin at the high level for each

connected device (including hysteresis) 0.2VDD 0.2VDD V

I2S DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 4)

Symbol Parameter Condition Min. Typ. Max. Unit

tLR LRCIN period (1/FS) 10.41 31.25 μs

tBL BCLK rising edge to LRCIN edge 50 ns

tLB LRCIN edge to BCLK rising edge 50 ns

tBCC BCLK period (1/64FS) 162.76 488.3 ns

tBCH BCLK pulse width high 81.38 244 ns

tBCL CBLK pulse width low 81.38 244 ns

tDS SDATA set up time 50 ns

tDH SDATA hold time 50 ns

Note 2: Thermal dissipation is limited by package type and PCB design. The external heat-sink or system cooling method should be adopted

for maximum power output.

Note 3: Measured with A-weighting filter.

Note 4: Guaranteed by design.

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