Kenwood TM-2550A Manuale utente

KENWOOD

MU-1,

MB-10,TU-7,

PG-2K,VS-1

M-2000A/E,TM-2530A

144Miiz

FM

TRANSCEIVER

Photo

is

TM-2550A.

CONTENTS

CIRCUIT

DESCRIPTION

.........

0.0000

ce

ae

2

TERMINAL

FUNCTIONS

.................0.

37

PARTS

LIST...

0...

0.

cc

eee

16

BLOCK

DIAGRAM

(TM-2550A,

TM-2530A)

......

38

DISASSEMBLY

........

2...

0.0

c

cee

eee

uaae

30

SCHEMATIC

DIAGRAM

(TM-2550A,

TM-2530A)

..

39

ADJUSTMENT

1.0.0.0...

0.

cee

ee

32

SCHEMATIC

DIAGRAM

(TM-2550E)

...........

40

PC

BOARD

VIEWS

BLOCK

DIAGRAM

(TM-2550E)...............

41

MIC

AMP.

(X59-1000-10)

...

2...

....

00008

36

LEVEL

DIAGRAM

......

0.0.0...

cc

eee

42

MIC

AMP.,S-METER

(X59-1010-10)

2.2.2.0...

36

MU-1

(MODEM

UNIT)

..............200000-

42

ALERT,

VACANT

CH.

(X59-1020-10)

..

2.2...

36

MB-10

(MOBILE

MOUNT)

..................

43

CENTER

DETECTOR

(X59-1030-10)

...

2.2...

36

TU-7

(TONE

UNIT)

..

2.2...

eee

44

SQUELCH

CONTROL

({X59-1040-10)

..

0.2.00.

36

PG-2K

(DC

POWER

CABLE)

.................

45

COMPOUND

UNIT

(X60-1280-XX)

.

2.0.0.0.

36

VS-1

(VOICE

SYNTHESIZER)..............-.

46

CONTROL

UNIT

(X53-1440-XX).....0.0..00.

36

PACKING

(TM-2550A/E,

TM-2530A)

...........

47

PLL

UNIT

(X50-2030-XX)

..

2

eee

ee

eee

36

SPECIFICATIONS

................

BACK

COVER

DISPLAY

UNIT

(X54-1860-10)

2...

...2.000,

37

FINAL

UNIT

(X45-1440-XX)

22...

2.000000.

37

TM-2550A/E,2530A

CIRCUIT

DESECRIPTION

TM-2550A

(K1,M1,M3)

TM-2550E

(T,W)

TM-2530A

(K2,M2,M4)

FINAL

UNIT

X45-

1440-10

X45-

1440-10

X45-

1440-11

PLL

UNIT

X50-2030-10

X50-

2030-51

X50-2030-11

X53-1440-10

(K1,M1)

CONTROL

UNIT

X53-1440-21

(M3)

X53-

1440-51

(T)

X53-

1440-61

(W)

X53-

1440-10

(K2,M2)

X53-

1440-21

(M4)

DISPLAY

UNIT

X54-1860-10

X54-

1860-10

X54-1860-10

COMPOUND

UNIT

X60-

1280-10

X60-

1280-51

X60-

1280-10

Table

1

TM-2550A/E,

TM-2530A

PC

board

chart

RX

SECTION

Signals

from

the

antenna

are

applied

to

the

FINAL

unit

(X60-1280-XX)

transmit

receive

swithing

circuit,

D2

and

D4.

In

receive,

diodes

D2

and

D4

are

reverse

biased

forcing

the

incoming

receive

signal

down

thru

L3

to

the

RA

(Re-

ceive

Antenna)

terminal.

There

the

incoming

receive

signal

is

then

coupled

to

the

COMPOUND

Unit

{X60-1280-XX).

The

signal

is

filtered

by

a

low

pass

filter

and

amplified

by

Q1

the

first

RF

amplifier,

a

GaAs

FET

:

3SK129(S).

The

amplified

RF

signal

is

then

mixed

with

the

LR

(Receiver

Local

Oscillator)

signal

in

the

first

mixer

Q2

:

3SK74(L)

to

obtain

the

First

iF

frequency

of

10.695MHz.

This

IF

signal

is

filtered

by

Helical

Resonator,

L4,

and

a

two

stage

MCF

(Monolithic

Crystal

Filter),

L8,

which

combine

to

provide

excellent

two-signal

characteristics

and

sensitivity.

The

First

IF

signal

from

the

MCF

is

then

amplified

by

the

First

1F

amplifier

Q3

:

2SC2668(Y}

and

applied

to

the

FM

iF

Amplitier/Mixer/Detector,

(C2

:

TA7761P.

This

signal

IC

mixes

the

IF

signal

with

the

10.24MHz

2nd

Locai

Oscil-

lator

signal

(L14}

to

obtain

the

2nd

IF

frequency

of

455kHz,

then

amplifies,

routes

the

signal

thru

external

filter

L16,

and

finally

convertes

it

into

the

received

audio

signal

with

the

internal

quadrature

detector.

The

2nd

Local

Oscillator

signal

from

L14

and

IC2

is

also

used

by

the

PLL

unit

as

a

Reference

signal.

The

detected

audio

output

from

|C2

is

applied

to

the

SQUELCH

CONTROL

(X59-1040-10),

and

to

the

de-

emphasis

circuit

R56

and

C99.

The

(de-emphasized)

audio

is

amplified

by

Audio

preamplifier

Q9

:

2SC2458(Y)

and

then

applied

thru

the

AF

GAIN

contro!

to

the

Audio

Amp-

lifier

[C1

;

¢PC1241H

which

drives

the

speaker.

The

noise

component

of

the

detected

audio

is

filtered

by

a

band-pass

filter,

in

order

to

obtain

a

frequency

of

appro-

ximately

30kHz

(which

is

well

outside

the

normal

voice

bandwidth)

and

then

amplified

by

the

noise

amplifiers

contained

inside

1C2.

This

amplified

noise

is

rectified

by

diodes

D6

and

D5

and

applied

to

O1

of

the

Squeich

Switch.

Q1

is

used

to

control

the

conduction

of

O2,

which

controls

AF

Preamp

Q9.

A

center-stop

tuning

circuit

is

provided

to

ensure

that

the

incoming

signal

is

actually

on

frequency

before

the

squelch

is

opened.

A

portion

of

the

455kHz

IF

signal

is

coupled

thru

the

secondary

of

L17

and

applied

to

CENTER

STOP

unit

(X59-1030-10)

where

Ceramic

Discriminator

L12,

and

Window

comparator

IC1

:

NJM4558M

are

used

to

deter-

mine

if

the

incoming

signal

is

actually

the

channel

center.

When

the

detected

signal

applied

to

the

window

compara-

tor

reaches

a

predetermined

level,

Q5

of

the

Squeich

Switch

will

be

turned

OFF

or

ON.

The

Squeich

Switch

determines

if

there

is

an

incoming

signal

at

the

same

time.

If

the

in-

coming

signal

is

at

the

proper

level,

and

on

frequency,

the

squelch

will

open

and

the

C.TUNE

indicator

in

the

LCD

display

will

turn

ON.

This

indicator

is

controlled

by

IC2,

the

main

microprocessor

on

ithe

CONTROL

unit

(X53-1440-XX),

thru

inputs

supplied

from

the

COM-

POUND

unit

via

the

BD

line.

During

Open

Channel

Scan-

ning

of

the

DCL

system

Q3, Q1,

and

Q2

of

the

Squelch

Switch

are

controlled

by

the

main

microprocessor

via

the

SOS

line.

During

DCL

operations

open

channel

search

thre-

shold

levels

are

controlled

by

VR3

of

the

Compound

ass’y.

Transistor

O6

of

the

Squelch

Switch,

is

used

to

prevent

the

Center

Stop

circuit

from

activating

during

Open

Channel

Scan

Operation.

Note

1:

The

Center

Stop

circuit

is

not

activated

during

Open

Chan-

nel

Scan.

Vv

Window

comparator

frequency

bandwidth.

o—

=

f

Pw

Frewuency

of

desired

Open

Channel

Channels

Interference

such

as

IMDfrom

strong

adjacent

channels

makes

the

use

of

the

Center

Stop

function

erratic

during

Open

channel

scan.

Fig.

1

Audio

Preamplifier

Q9

is

controlled

by

Q1

of

the

Alert,

Vacant

CH.

unit

(X59-1020-10)

during

Alert,

code

Squelch

and

Open

Channel

operations.

Li2

CFY455S

CIRCUIT

DESECRIPTION

TM-2550A/E,2530A

Input/Output

characteristics

Principle

of

operation

of

window

comparator

of

L12.

8R

CENTER

DATECTOR

9

(X59-1030-10)

+e

eo

Et:

4.1V—0

(4.06V)

|

“

1

6

se

i

-

7

1

,

Rt

1

ae

et

Ct

5

101

(2/2)

Et

E2

et

&1

£2

y

OR?

ei=4.1Vi0e

1C1(2/2)

q

Wr

C4

01

Qi

b>

]}~

C4172)

oe

beg

4iv_

23

2

g

=

|

J.

E2

3

-e

q

3

@

:

Set

voltage

at

time

when

.

82V

Ns

detuning

from

3kHz.

.

[

ST

(About

0.04V)

Ei

e2

et

—_

10

;

4

ry

=

a¢

Center

detection

od

Set

to

“H”

when

signals

received

from

|

outside

is

within

about

+

3kHz.

BD

:

Center

stop

signal

Set

to

“L"

when

in

SOL

OPEN

mode

at

center.

z

[CONT-14

-

BD]

e

8R

n

L

+4

SOL

CONTROL

3

9

{(X89-

1040-10)

§

at

|

cunemmens

a

Q6

tusned

on

when

in

SQL.

OPEN

4

turned

on

when

mode

while

searching

vacant

channels.

in

SQL

OPEN

mode

Lis

=

R1

R5

at

center.

a

NOISE

FILTER

‘|

as

a

7

|

D5

10

RG

1

Q3

turned

on

NOISE

when

in

SQL

:

P

FM

DET

5

turned

on

when

signal

|

iF

AM

KY

AMP.

H

+

Set

to

“H"

when

in

OPEN

mode.

received

from

outside

is

© °

SQL

OPEN

mode.

at

center.

Le

———-

a

5

”

Set

to

about

OV

when

in

:

Ic.

SQL

CLOSE

or

TX

mode.

[

”

.

omeatiien.®

-

;

I

NOISE

DET.

|

awit

th.

Q39

is

cut

off

for

muting

when

in

SQL

|

6

x

CLOSE,

TX,

or

ALERT

mode.

1

|

°

ox

|

,

”

o

|

C103

«C104

At

1

A

se

F

PA

|

c100

3

+

im

“

‘

7

|

AF

VR

10

—

a1

Q2

turned

on

when

searching

Q1

is

turned

on

and

O9

vacant

channels

to

change

is

cut

off for

muting

when

°

Q3

Q2|

>”

from

SQL

to

VR3.

in

TX

or

ALERT

mode.

Set

to

“L"

normally.

mode.

Set

to

“H’

when

searching

vacant

channels

in

DCL

04

RS

OPERATION

mode.

>

a

Jz

|

Q3

turned

off

when

RT

2

T

Sas

searching

vacant

—ed

channels.

ZL

°

7

ALERT,

VACANT

CH.

(X§9-

1020-10)

|

Fig.

2

Center

datector,

Alert,

Vacant

CH,

SQL

control

circuit

TM-2550A/E,2930A

CIRCUIT

DESECRIPTION

Item

Rating

Item

Rating

Nominal

center

frequency

(fo)

|

10.695MHz

Nominal

center

frequency

(fo)

|

455kHz

Pass

bandwidth

+7.5kHz

or

more

at

3dB 6dB

bandwidth

+6kHz

or

more

+25kHz

or

less

at

40dB

£45k

Hz

or

less

at

6OdB

Attenuation

bandwidth

1.

70dB

or

more

within

+1MHz

2.

Spurious

jevel

=

40dB

or

more

at

fo—fo

+

500kHz

3.

Spurious

level

=

80dB

or

more

at

fo—(910kHz+10kHz)

Guraranteed

attenuation

Ripple

1.0dB

or

less

Loss

1.5dB

or

less

Impedance

3kQ/0pF

Table

2

MCF

(L71-0216-05)

COMP

unit

L8

+12.5kHz

or

more

3dB

or

less

6dB

or

less

35dB

or

more

50dB

bandwidth

Ripple

(within

455+5kHz)

Loss

Guaranteed

attenuation

(within

455+100kHz)

Input

and

output

impedance

2.0k2

Table

3.

Ceramic

filter

(L72-0315-05)

COMP

unit

L16

®

@®

t

!

Qio

r

if

®

Qis6

0

2

Ris

«

o

°

R13

:

a

i

2

+

7

aia

Qi?

Qi8

©

N

Q3

Py

rs

ae

a

OVER

az

ais

VOLTAGE

x4

N

t

&

4

ant

°

SURGE

pia

|

01S

pte

©

PROTECTION

4

Q5

a7

o

38

Sr

m

at

=

a2

a4

RG

c1

5%

Jats

W-o

1

¢

wo

°

,

'

|

a

Qi2

‘

Q6

Qs

S

aii

o20

+5)

t

13

THERMAL.

SHORT

rd

SHUT

ciRCcUIT

oye

DOWN

PROTECTION

~

210

2

z=

Ome

ne

wo

=3

Sa

Se

¢£

abr

te

z>

x

«

lL“)

¥28

Fig.3

PC1241H

Equivalent

circuit

(COMP

unit

1C1)

TX

SECTION

Incoming

microphone

audio

from

the

DISPLAY

unit

(X54-1860-10

C/3)

is

amplified

by

Q8

:

2SC1775(E).

This

amplified

audio

is

then

buffered

by

buffer

amplifier

Q7

:

2SC2458(Y)

and

applied

to

D2

:

188181

of

the

MIC

AMP/S

METER

unit

(X59-1010-10)

for

limiting.

The

signal

is

then

amplified

by

a

portion

of

1C1

:

NJM4558M

on

the

MiC

AMP/S

METER

unit.

D2

of

the

MIC

AMP

unit

(X59-1000-10)

provides

additional

limiting.

The

micro-

phone

audio

is

filtered

by

a

2

stage

active

LPF,

IC1

:

NJM4558M

and

applied

to

varactor

diode

D3

:

1$2208

in

the

PLL

unit

(X50-2030-XX)

for

phase

modulation

of

the

transmit

VCO,

08.

The

phase-modulated

FM

signal

is

amplified

by

driver

tran-

sistors

Q10

:

2SC2688(Y),

Q11

:

28C2347

and

Q12

:

2SC2538-22-A

(TM-2530)

or

2SC3019

(TM-2550)

and

applied

to

the

FINAL

unit

(X45-1440-10

:

TM-2550A/E

or

4

X45-1440-11

:

TM-2530A).

This

signal

is

amplified

by

the

Hybrid

Final

Amplifier

Module

Q1

M57737

(TM-2530A)

or

M57726

(TM-

2550A/E)

and

applied

to

the

antenna

via

the

transmit/

receive

switching

diode

D2.

During

transmit,

forward

bias

is

applied

to

D2

allowing

the

transmit

signal

to

pass.

Diode

D3

is

also

forward

biased

during

transmit.

The

value

of

L3

was

selected

to

present

a

high

impedance

to

the

transmitted

signal.

Any

of

the

transmit

signal

that

passes

thru

L3

is

shunted

to

ground

thru

D3

to

protect

the

receiver

circuits

and

prevent

feedback.

Once

the

signal

has

been

passed

thru

D2

it

proceedes

thru

the

LPF

and

to

the

antenna.

The

APC

(Automatic

Protection

Circuit)

on

the

FINAL

unit

consists

of

two

circuit,

a

negative

feedback

circuit

that

senses

output

power

and

an

SWR

protection

circuit.

TM-2550A/E,2530A

CIRCUIT

DESECRIPTION

The

negative

feedback

circuit

samples

the

transmitted

signal,

rectifies

this

signal

with

D4,

and

applies

the

rectified

signal

to

NF

GAIN

amplifier

Q6

:

2SC2458(Y).

This

amp-

lifier

supplies

a

signal

to

Differential

Amplifiers

Q4

and

Q5

:

2SC2458(Y)

which

control

the

bias

applied

to

the

PA

module

2,

and

driver

transistor

Q12

of

the

PLL

unit,

via

bias

regulators

Q2

:

2SD1406(Y)

and

O3

:

2SA1015(Y).

|

if

High/Low

power

swithing

is

accomplished

by

applying

a

ground

to

number

1

of

connector

(2)

on

the

FINAL

unit.

This

causes

VR3

to

act

as

a

voltage

divider

that

cont-

rols

the

condution

of

NF

GAIN

amplifier

Q6.

L

Reflected

power

is

coupled

thru

D5

on

the

FINAL

unit

and

is

used

to

control

the

conduction

of

Q7.

This

transistor

function

like

Q6

to

control

differential

amplifers

Q4

and

O5,

and

thus

the

bias

applied

to

the

Power

Amplifier.

Item

Symbol

|

Tc(°C)

Condition

Rating

Operating

Vee

25

17V

DC

current

Iec

25

7A

Operating

case

temp.

|

Tc

(op)

—30~

+

110°C

Storage

temp.

Tstg

—40~

+

110°C

Power

input

25

Zg

=

Zi

=

502

0.4W

Power

output

Po

25

Zg

=

ZI

=

502

40W

Table

4

M57737

Max.

rating

(TM-2530A

Final

unit

01)

lik

Lo

Le

@IinPpuT

@Vcci

@Vcc2

@MouT

@Gnod

Fig.4

M57737

Equivalent

circuit

Item

Symbol

|

Te

(°C)

Rating

Operating

voltage

Vee

25

17V.

DC

current

icc

25

14A

Operating

case

temp.

|

Tc

(op)

—30~

+

110°C

Storage

temp.

Tstg

—40~

+

110°C

Table5

M57726

Max.

rating

(TM-2550A/E

Final

unit

Q1)

Value

Item

Symbol

|

Tc

(°C)

Condition

Min.

Typ.

Vcc

=

12.5V.

F

=

144~148MHz,

=O0.4W,

ZL

=

ZG

=

502

Power

output

Po

25

43W

47W

Vee

=

12.5V,

F

=

144~148MHz,

=

0.4W,

ZL

=

ZG

=

502

Total

efficiency

nT

25

50%

54%

Table

6

™M57726

Electrical

characteristic

H

1,

@in

@vcci1

@Vcc2

Mout

Ono

Fig.5

M57726

Equivalent

circuit

PLL

CIRCUIT

The

PLL

circuit

is

divided

into

two

main

loops

:

transmit

and

receive.

Receive

PLL

Loop

The

signal

generated

by

the

RX

VCO

(Voltage

Controlled

Oscillator)

Qi6

:

2SK192A(GR)*P

is

applied

to

buffer

amplifier

Q17

:

2SC2668(Y)

and

mixed

with

the

HET

(Heterodyne)

signal

by

Q21

:

2SC2668(Y)

where

it

be-

comes

the

PLL

IF

signal

(K,M

13.015

to

15.010MHz,

T,W

12.865

to

19.86MHz).

This

PLL

IF

signal

is

then

amplified

by

020

:

2SC2668(Y}

and

applied

to

the

Phase

Detector

{C2

:

MC145155P*K

where

it

is

divided

to

obtain

a

5kHz

signal.

The

divide

ratio

is

determined

by

Serial

Data

from

the

CONTROL

unit.

This

5kHz

signal

is

compared

with

the

5kHz

reference

signal

obtained

by

dividing

the

10.240

MHz

Reference

signal.

The

Phase

Detector

compares

the

phase

of

these

two

signals

and

transmits

an

error

control

signal

to

the

VCO.

The

cont-

rol

signal

is

filtered

by

an

Active

Low

Pass

filter

composed

of

013

:

2SK30A(O)

and

Q14:

2SC2458(Y)

to

remove

any

AC

fluctuations

to

obtain

a

DC

correction

voltage.

The

correction

voltage

is

used

to

change

the

capacitance

of

Varactor

Diode

D5

:

1SV50,

which

varies

the

output

of

the

RX

VCO

to

lock

it

on

frequency.

If

the

phase

difference

is

too

great

to

be

corrected

by

the

control

voltage

applied

to

D5,

an

unlock

signal

is

generated

by

the

Phase

Detector.

This

signal

turns

OFF

Q15

:

2SC2458(Y)

which

turns

OFF

output

amplifier

O18

:

2SC2668(Y)

to

prevent

operation

outside

the

authorized

limits.

The

PLL

HET

Oscillator,

Q19

:

2SC2668(Y)

oscillates

at

39.48MHz.

This

signal

is

applied

to

frequency

tripler

Q22

:

2SC2688(Y)

to

obtain

a

signal

of

118.44MHz

which

is

applied

to

mixer

Q21.

TM-2550A/E,2530A

CIRCUIT

DESECRIPTION

Transmit

PLL

Loop

The

signal

generated

by

the

TX

VCO

O8

:

2SK125

(KM

142.00

to

148.995MHz,

T,W.

144.00

to

145.995MHz}

is

mixed

with

the

RX

PLL

output,

by

Q7

:

2SC2688(Y)

and

applied

to

the

Transmit

Phase

Detector

IC1

:

MC145151P.

This

signal

and

the

10.240MHz

signal

from

IC2

are

divided

by

512,

to

obtain

20kHz.

These

two

signals

are

compared

and

an

error

correction

signal

is

applied

to

the

Active

Low

Pass

filter

Q3,

Q4

and

O5

:

2SC1775(E).

Comparision

at

a

frequency

of

20kHz

provides

shorter

response

times,

a

real

necessity

in

transmit.

The

DC

correction

voltage

from

the

LPF

is

used

to

contro!

varactor

diode

D2

:

1SV50.

The

divide

ratio

is

increased

by

91

during

transmit

opera-

tions.

This

causes

the

TX

VCO

frequency

to

be

locked

at

a

frequency

455kHz

higher

than

the

RX

VCO

frequency

which

prevents

internal

mixing.

When

an

error

occurs

that

is

greater

than

the

correction

voltage

limits

an

unlock

signal

is

generated

by

!C1.

This

signal

controls

the

conduction

of

Q1

:

2SC2458(Y)

which

controls

Q2

:

2SA1048(Y)

to

stop

transmissions.

Q2

interrupts

the

bias

of

the

TX

driver

stage..

vppo2—>

RA2O7—*

cE

LOCK

8

VssC

7

RAI

Org

12

x

8

ROM

REFERENCE

DECODER

DETECT

-—C)

LD

OSC

OUT

|

Ledbetter

ey

1

OSC

IN

7

2b}

+2

bs

12-BIT

+

R

COUNTER

ER

PHASE

6

¢y_

|

DETECTOR

F-O

PD

OUT

A

t

4

REF

OUT

PHASE

L—OoR

DETECTOR

|

3

9

B

r—O

oV

FIN

14-BIT

+

N

COUNTER

o_o

voo—w—

-ttttitifittiit

P

ENABLEO

LATCH

>|

LATCH

f—OswW!

4

TEEFEEEtETTTT

tf

DATAO—

>

J

>.

Cc

14-BIT

SHIFT

REGISTER

7a

ER.

crock

ol?

Fig.6

MC145155P«K

Block

diagram

(PLL

unit

IC2)

rao

Oe

12

x8

ROM

REFERENCE

DECODER

Lock

128,15

OSC

OUT

RAO

02>

DETECT

teed

di

ty

osc

Ino=

=2

bs]

12-BIT

+R

COUNTER

PHASE

4

Vss

oO

DETECTOR

-—©

PD

OUT

Vppot>

{

9

FINO!

os

14-BIT

+

N

COUNTER

DE

eOTOR

fe

B

FEEEEEPT

PTI

10

TRANSMIT

94

—OfV

RECEIVE

O

TRANSMIT

OFFSET

ADDER

EEEEEEDEERNEAR

N13

-°

N11

N44

N2

Fig.

7

MC145151P

Block

diagram

(PLL

unit

IC1)

TM-2550A/E,2530A

CIRCUIT

DESECRIPTION

—

118.44MHz

—-39.48MHz

——

a21:

a22

:

aig:

Tic2:

mc145156P+K

2Sc2668(Y)

2SC2668(Y)

28C2668(Y)

142,0~148.995MHz

(K,M)

l

144.0~145.995MHz

(T,W)

|

j

131.308~138.300MHz

(K,M)

l

133.305~135.300MHz

(T,W}

5kHz

,

|

P.D

LPF

}-

reo

{MIX

1/2048}

l

|

O13:

28K30A(0)

a6:

_y

ata:

2802458(Y)

2SK192A(GR}+P

N

:

2573~3972

(RX)

(K,M)

2664~4063

(TX)

(KM)

|

135

969~138.755MHz

(K,M)

2973~3360

(RX)

(TW)

|

1

33'769~135.755MHz

(TW)

3064~3451

(TX)

(T,W)

:

10,695MHz

10.24MHz

TMP47C46N-9042

(

:

142.0~148.995MHz

(K,M)

10.24MHz

ors

144,0~145.995MHz

(T,W)

|

Q7

:

28C2668(Y)

|

-

TX

20kHz

|

Q3~5:

Qs

:

28C1775(E)

2SK125

PLL

UNIT

=

el

Fig.8

Frequency-related

block

diagram

(7.2V)

(7.6V)

(8.3V)

(*8.3V)

(*8.35V)

(*OV)

*:

UNLOCK

To

RF

AMP

(Q10—12)

To

COMP

unit

(0.9V)

ist

MIX

FET

Q2

(*0V)

(8.4V)

(*8.4V)

Z

8T

(7.2V)

(*0V)

NORMAL

UNLOCK

»:

UNLOCK

4.5V

4V

28

‘-

a

7

58V

ic1

15V

*1.3V

a]

NORMAL

UNLOCK

1

4

ov

ov-

:

8 6

+f

0.2ms

+f

0.3ms

50us

100us

4Vv

——|

a

>

1c2

v

|

I

|

7

2v

2V

W—Wwa—|

ACTIVE

FILTER

™

TX

VCO

|

10.24MHz

ov

From

1C2

(10.24MHz)

TX

section

RX

section

Fig.9

Unlock

circuit

TM-2550A/E,2530A

CIRCUIT

DESECRIPTION

CONTROL

UNIT

(X53-1440-XX)

The

CONTROL

unit

uses

two

Microprocessors.

the

Main

Microprocessor

1C2

:

TMP47C46N-9042

and

Auxilliary

Microprocessor

[C3

:

uPD75008HC-056.

Both

utilize

4

bit

architecture

and

have

4K

Bytes

of

ROM

available.

The

Main

Microprocessor

controls;

frequency,

offset,

tone,

memory

frequency,

key,

switch,

encoder,

frequency

dis-

play,

DCL

system

and

the

Auxillary

Microprocessor.

The

Auxilliary

Microprocessor

controls;

the

voice

synthesizer,

display/contrl/and

memory

for

telephone

number

func-

tions,

tone

frequencies

(K,M),

audio

oscillator,

and

digital

signal

conversion

and

analysis

processing

for

DCL

system.

The

Main

Microprocessor

utilizes

a

serial

interface

bus

to

the

Auxilliary

processor.

A

CMOS

static

RAM,

IC6

:

TC5047AP-1

with

a

capacity

of

1K

x

4

bits,

is

used

for

external

memory

storage

of

operator

programmed

data

such

as

memory

frequencies

and

telephone

number

data.

It

also

functions

as

a

data

buffer

when

exchanging

data

bet-

ween

the

Main

and

Auxilliary

processors.

Memory

address-

ing

is

performed

by

1C5

:

TC40H374P

with

read

and

write

operations

being

handled

by

the

Data

Bus.

¢.sa

|

M.CH

/|

KOO

a

KO1

SW

RETURN

A,

Ga

&

§

D

mM

a

m

i

we!

=z

ioe

>

ie

KO2

F.LOCK

vA

DCL

J

SCAN

wal

4

Fd

KO3

#

RC2

R41

R40:

SW

SCAN

OUTPUT

(ACTIVE

LOW)

Fig.

10

Diode

matrix

Switch

Section

With

a

few

exceptions

most

switch

inputs

on

the

front

panel

are

arranged

in

a

diode

matrix.

The

Main

Micropro-

cessor

reads

the

inputs

via

a

keyboard

status

scan

system.

This

system

determines

which

key,

if

any,

has

been

de-

pressed.

The

diode

matrix

is

illustrated

in

Fig.

10.

The

PHONE

switch

(K,M),

P.MR

switch

(TW)

TONE

switch,

PTT

switch,

UP

switch

and

DOWN

switch

all

supply

inputs

directly

to

the

Main

Microprocessor.

Keyboard

section

Fig.

11

iHustrates

the

keyboard

section

circuit

diagram.

The

keyboard

receives

scan

pulses

from

the

Main

Micropro-

cessor

ports

P10

thru

P13.

The

current

keyboard

status

is

-

returned

via

ports

R70

thru

R73.

Pull-up

resistors

of

P10

thru

P13

are

controlled

by

port

R90.

Keyboard

status

is

scanned

when

R90

is

pulled

up

from

logic

low

by

QO3

:

DTA114YF.

Display

section

Fig.

11

shows

the

layout

of

the

LCD.

The

LCD

driver

(Keyboard

ass'y)

is

controlled

via

8

data

lines

and

4

control

lines

on

a

parallel

bus

system

by

the

Main

and

Auxilliary

microprocessors.

Data

transfer

is

possible

only

when

the

CS

line

is

Low

and

in

conjuction

with

the

teading

edge

of

the

WE

pulse.

The

DCL

and

COS

LED's

are

lit

by

transistors

O04

and

O5

which

are

controlled

by

the

Main

Microprocessor.

TM-2550A/E,2530A

CIRCUIT

DESECRIPTION

—

|

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Fig.

11

Keyboard

section

circuit

diagram

9

TM-2550A/E,2530A

10

CIRCUIT

DESECRIPTION

DTMF

circuit

(K,M

Type)

The

DTMF

(Dual

Tone

Multiple

Frequency)

signal

is

gene-

rated

by

IC4

:

LR4087

on

the

CONTROL

unit.

Power

for

the

tone

generator

is

obtained

from

the

8T

(8

volts

on

transmit)

line.

During

receive

the

IC

is

grounded

preventing

unwanted

tone

generation.

During

transmit

the

non-exclusive

port

R9O

is

a

logic

High,

causing

pull-up

resistors

P10

thru

P13

to

open

allowing

the

DTMF

signals

to

be

generated

by

pressing

one

of

the

key-

board

keys.

During

automatic

transmission

of

telehphone

number

infor-

mation

port

R90

is

a

logic

Low,

connecting

pull-up

resistors

P10

thru

P13.

P10

thru

P13

apply

a

logic

High,

and

P70

thru

P73

a

logic

low,

so

that

the

desired

DTMF

signals

are

generated.

While

the

DTMF

signal

is

being

generated

IC4

(CONTROL

unit)

mutes

the

normal

transmitted

audio.

_—_

—_

.

—

a

ee

i

5V

-

IC4

:

LR4087

10

osc

aor

|

MES

MEOUT

“IN

z

|

ak

42

ar:

os

O13

yy

3

-_-—

|

—f

84

EH

_*

ie

Rt

OSC

OUT

0

4

4S

fs

|

O14

43

16

|

oe

eee

kt

R2

TOOUTE

>

TT

|

7

|s

|9

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j

O15

yo

care

L

J

mmm

rm

1

R3 C3

|

Sy

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oy

Us

j

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4

L2

M

9

rs

;

OG

,,

car

|

mM

—_t}

So

oy

co

Ce

R4

Ct

|

.

|

\

t

|

K,MTYPE

ONLY

|

‘

|

oY

P10

P11

P12

P13.

R73

R72

R71

R70

(K1)

(K2) (K3)

(K4)

(KB) (K7)

(K6)

(KS)

Yv

v

KEY

SCAN

KEY

RETURN

R30

Fig.

12

DTMF

circuit

R1

R2

R3

R4

VE

ove

141312)

1

—

— —

©

-

——7

ANA

Vt

MUTE

|

mM

KB>—]

50

OUT

——

Why

|

$—w-

|

[

yggare

var

ve

|

SIGN

D/A

|

ROW

WAVE

b+

TER

COUNTER

Jw—

COUNTER

CONVER

TONE

OUT

COLUMN

SIGN

D/A

Ve

COUNTER

ja—@

COUNTER

|

CONVERTER

|

KEYBOARD

__f

VKB

|

Locic

Le

yvxs

V+

XMTR

|

<M

:

sw

AAO

48)

SINGLE

TONE

Ww

~

INHIBIT

Wye

VV

—

3445

HO

—

eo

———

—

IJ

ci

c2 C3

C4

Fig.13

LR4087

Block

diagram

(Control

unit

1C4)

K,

M

type

only

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