Lattice USB3 Manuale utente

August 2014

EB88_1.0

Lattice USB3 Video Bridge Development Kit

User’s Guide

Lattice USB3 Video Bridge Development Kit

Introduction

The Lattice USB3 Video Bridge board allows designers to investigate and experiment with the features of the

LatticeECP3™ Field-Programmable Gate Array device in applications of transporting video and audio data through

the Universal Serial Bus (USB) 3.0 link. The Lattice USB3 Video Bridge board is the hardware platform of the Lat-

tice USB3 Video Bridge Development Kit. Combined with the control and configuration application software and

drivers, the features of the Lattice USB3 Video Bridge board can assist design engineers with rapid prototype and

validation of their specific USB3 Video Bridge designs. This guide is intended to be referenced in conjunction with

the RD1203, Lattice USB3 Video Bridge Reference Design User's Guide to demonstrate the capability and perfor-

mance of LatticeECP3 FPGA.

Features

Key features of the Lattice USB 3.0 Video Bridge Development Kit include:

• SuperSpeed USB 3.0 Interface over Cypress EZ-USB FX3 (CYUSB3014) IC

• HDMI interface over Analog Devices ADV7611 IC

• Embedded SDI Receiver interface with TI LMH0394 Cable Equalizer

• Si5338 programmable clock generator

• LatticeECP3-17 FPGA programmed with USB3 Video and Audio bridge function

• Expansion connector for Image sensors using SubLVDS or MIPI CSI-2

• Selectable expansion VCCIO

• Selectable power supply (USB or Auxiliary 5V)

• Fly-wire ispDownload cable connection for JTAG fast program and Reveal Analyzer

• SPI serial flash controlled by the FX3 USB controller

• FPGA configuration at startup by the FX3 via the ispCONFIG SPI interface

• I2C and SPI bus for onboard device controls from the FX3

• FX3 JTAG Connector

• 2-pin GPIO debug connector (LVTTL) useful for I2C or UART

General Description

The Lattice USB3 Video Bridge Development Kit is built around the LatticeECP3-17EA 328-ball csBGA FPGA

device. The board with the FPGA, peripheral devices and connectors provide a seamless USB3 bridge function for

video streaming and capturing applications utilizing the USB 3.0 USB Video Class (UVC) standard. It also supports

multi-channel I2S PCM audio streaming through the same USB3 link. The parallel video and audio interface from

the ADV7611 HDMI Receiver, the embedded CML SERDES Receiver interface, and differential I/Os on the sensor

expansion header are useful for evaluating various Lattice IP cores for video interfacing, as well as the USB 3.0

UVC bridge design. A number of test points are provided to validate various power and configuration status.

Figure 1 shows the conceptual connections between LatticeECP3 FPGA device and other peripheral components

of the USB3 Bridge board.

The contents of this user's guide include top-level functional descriptions of the various portions of the board,

descriptions of the on-board connectors, diodes and switches and a complete set of schematics.

Lattice USB3 Video Bridge Development Kit

Figure 1. Lattice USB3 Video Bridge Board Block Diagram

Initial Setup and Handling

The following is recommended reading prior to removing the evaluation board from the static shielding bag and

may or may not apply to your particular use of the board.

CAUTION: The devices on the board can be damaged by improper handling.

The devices on the evaluation board contain fairly robust ESD (Electro Static Discharge) protection structures

within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example

of ESD characterization requirements). Even so, the devices are static sensitive to conditions that exceed their

designed in protection. For example: higher static voltages, as well as lower voltages with lower series resistance

or larger capacitance than the respective ESD specifications can potentially damage or degrade the devices on the

evaluation board.

As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while han-

dling the evaluation board when it is removed from the static shielding bag. If you will not be using the board for a

while, it is best to put it back in the static shielding bag. Please save the static shielding bag and packing box for

future storage of the board when it is not in use.

When reaching for the board, it is recommended that you first touch the outside shield portion of the SDI connector.

This will neutralize any static voltage difference between your body and the board prior to any contact with signal

I/O.

CAUTION: To minimize the possibility of ESD damage, the first and last electrical connections to the board should

always be from test equipment chassis ground to the pin 1 of the J3 header.

Quad A

Ch0 Ch1 Ch2 Ch3 Ref

clk

EZ USB FX3

Bank 0

Bank 8

Bank 1

Bank 2

LatticeECP3-17EA

cs328BGA

Bank 7

Bank 6

Bank 3

ADV7611

100 MHz

SDI

Expansion

connector

Lattice USB3 Video Bridge Development Kit

Before connecting signals or power to the board, attach a cable from chassis ground on grounded test equipment

to the to the pin 1 of the J3 header. Connecting the board ground to test equipment chassis ground will decrease

the risk of ESD damage to the I/O on the board as the initial connections to the board are made. Likewise, when

unplugging cables from the evaluation board, the last connection unplugged, should be the chassis GND connec-

tion to the evaluation board GND. If you have a signal source that is floating with respect to chassis GND, attempt

to neutralize any static charge on that signal source prior to attaching it to the evaluation board.

If you are holding or carrying the board when it is not in a static shielding bag, please keep one finger on the out-

side shield portion of the SDI connector. This will keep the board at the same voltage potential as your body until

you can pick up the Dstatic shielding bag and put the board back in it.

Electrical, Mechanical and Environmental Specifications

The nominal board dimensions are 99 mm x 69 mm. On the physical board itself, connectors include pin 1 indica-

tors as a dot, or a number “1” beside the pin 1 on the outer layer silk screen. The environmental specifications are

as follows:

• Operating temperature: 0 °C to 55 °C

• Storage temperature: -40 °C to 75 °C

• Humidity: <95% without condensation

•5VDC

Functional Description

Figure 2. Lattice USB3 Video Bridge Board, Top View

Micro-USB 3.0

Super Speed

Connector

Board

Power Select

Auxillary 5 V

Power

Lattice ECP3-17EA

cs328BGA Package

(10 mm X 10 mm)

Cypress EZ-USB FX3

CYUSB3014

(10 mm X 10 mm csBGA)

Analog Devices ADV7611

HDMI 1.4a Receiver

HDMI

1.4a Input

SDI Equalizer

(TI)

SDI Input

SD-, HD-, 3G-SDI

Expansion

Connection

SubLVDS, MIPI

Expansion

VCCIO Select

Lattice USB3 Video Bridge Development Kit

LatticeECP3 Device

This board features a LatticeECP3-17 FPGA with a 1.2 V DC core in a 328-ball csBGA 10 mm x10 mm package. A

complete description of this device can be found on the Lattice web site at www.latticesemi.com/prod-

ucts/fpga/ecp3.

USB3 Connector (J8)

The board is powered and communicates with the USB 3.0 Host through an USB 3.0 Micro b connector/receptacle.

It is connected to the host with the provided USB 3.0 A-to-Micro b cable.

Auxiliary Power Connector (J9)

The board can be alternately supplied by a single 5 V DC power supply at J9. On-board step-down switching regu-

lators then provide the necessary supply voltages: 3.3 V, 2.5 V, 1.8 V, 1.2 V. For proper operation, the 5 V DC power

applied at J9 should be within the range of +4,75 V min. to +5,25 V max. The requirements for the J10 power jack

itself are listed in Table 1.

Table 1. Auxiliary Power Jack J9 Specifications

Power Supplies

The on-board switching and linear regulator output voltages can be measured at test points located around the

board as shown in Table 2.

Table 2. Test Points for On-Board Regulator Voltages

Each of the step-down switching regulators, U7, U8 and U9, incorporate typical resistor divider voltage feedback to

divide down the regulator output voltage and compare it against an internal reference voltage. The regulator then

adjusts the output voltage higher or lower such that the resistor divided voltage matches the internal reference. By

doing this, the regulator output voltage remains at a constant voltage value independent of the load driven. Each

regulator output voltage follows this equation:

Vout= (1 + resistor ratio) x (regulator internal reference voltage)

See the LT3685 and LTC3621 device data sheets for additional details about these devices.

The 1.8 V regulator (U10) is a low dropout linear type regulator with an adjustable output voltage which is set using

the external resistive divider. The output voltage is given by the formula:

Vout= (1 + resistor ratio) x (Vadj)

where Vadj is feedback voltage.

Polarity Positive Center

Inside diameter 0.1'' (2.5 mm)

Outside diameter 0.218'' (5.5 mm)

Current Capacity Up to 2.5 A

Supply Regulator Test Point Resistor Ratio Comment

5.0 V - TP2 NA Input voltage

3.3 V U8 TP5 R73/R76

2.5 V U9 TP6 R77/R80

1.8 V U10 TP7 R82/R83

1.2 V U7 TP3 R70/R72

1.2 V (SERDES) U11 TP8 NA

Lattice USB3 Video Bridge Development Kit

See the LP38511 device data sheet for additional details about this device.

The SERDES 1.2 V regulators (U11) are low dropout linear types that deliver a constant 1.2 V output voltage when

tors do not generate switching noise, so they are a good choice for powering the LatticeECP3 SERDES to give the

lowest jitter generation. Also, U11 does not use resistor divider networks to set the output voltage, instead it is set

up to directly copy its own internal 1.215 V reference voltage to its outputs. The U11 regulator outputs are available

for testing at test points TP8 and TP9. See the LT3029 device data sheets for additional details about this device.

When using the various I/O test points located around the board, be sure to not exceed the LatticeECP3 Family

Data Sheet specified absolute maximum rating for Output Supply Voltage VCCIO range of -0.5 V to +3.75 V, or

damage to the device may occur. Also, for I/O input capability of the various I/O standards supported by the

LatticeECP3 sysIO structures, see the LatticeECP3 sysIO Usage Guide.

Cypress EZ-USB FX3 (U5)

Cypress’s EZ-USB FX3 is the next-generation USB 3.0 peripheral controller, providing integrated and flexible fea-

tures.

FX3 integrates a fully configurable, parallel, general programmable interface called GPIF II, which can connect to

any processor, ASIC, or FPGA. It provides simple connectivity to popular interfaces, such as asynchronous SRAM,

asynchronous and synchronous address data multiplexed interfaces, and parallel ATA.

FX3 has integrated the USB 3.0 and USB 2.0 physical layers (PHYs) along with a 32-bit ARM926EJ-S micropro-

cessor for powerful data processing and for building custom applications. It implements an architecture that

enables 375-MBps data transfer from GPIF II to the USB interface.

For more information on the EZ-USB FX3, please refer to the EZ-USB FX3 Datasheet

http://www.cypress.com/?docID=44322.

GPIF II Interface

The GPIF II interface implements the Slave FIFO signaling to receive the UVC and UAC packeted streaming data

from the LatticeECP3. For more information about the Slave FIFO interface, please consult the EZ-USB FX3 Data-

sheet technical reference manual http://www.cypress.com/?docID=44322. The signal connections between the EZ-

USB FX3 and the Lattice ECP3 Device are shown in Table 3.

Table 3. LatticeECP3(U1) connections to EZ-USB FX3 (U5) GPIF II interface

Signal sysIO Bank LatticeECP3 BGA Ball

EZ-USB FX3

Interface Signal

sf_data[0] 8 D18 dq[0]

sf_data[1] 1 A12 dq[1]

sf_data[2] 0 B10 dq[2]

sf_data[3] 8 L17 dq[3]

sf_data[4] 8 A16 dq[4]

sf_data[5] 1 A11 dq[5]

sf_data[6] 8 H18 dq[6]

sf_data[7] 8 D17 dq[7]

sf_data[8] 8 J18 dq[8]

sf_data[9] 8 F17 dq[9]

sf_data[10] 8 J17 dq[10]

sf_data[11] 8 F19 dq[11]

sf_data[12] 8 J19 dq[12]

Lattice USB3 Video Bridge Development Kit

SPI Serial Flash (U12)

The U12 SPI Flash device used on this board is a 16-pin, 16-Mbit device, operated by the EZ-USB FX3. It is suffi-

cient to store both the EZ-USB FX3 Firmware and the LatticeECP3 Bitstream. The EZ-USB FX3 will boot from the

SPI flash, then read out and download the LatticeECP3 Bitstream over the Slave SPI sysCONFIG interface. The

SPI Flash device is an STMicro SPI-M25P16 in an 8-pin package.

LatticeECP3 IO Bank Voltages

Most of the bank voltages on the LatticeECP3-17 device (U1) have been hard-wired to specific power supply val-

ues, except for the bank 2 which can be set to different voltage levels to support various sensor and camera inter-

faces through the expansion connector J1. The voltage assignment is shown in Table 4.

sf_data[13] 1 B13 dq[13]

sf_data[14] 8 G18 dq[14]

sf_data[15] 1 A14 dq[15]

sf_data[16] 0 C7 dq[16]

sf_data[17] 0 B8 dq[17]

sf_data[18] 0 C6 dq[18]

sf_data[19] 0 B4 dq[19]

sf_data[20] 0 B7 dq[20]

sf_data[21] 0 A7 dq[21]

sf_data[22] 0 A6 dq[22]

sf_data[23] 0 B5 dq[23]

sf_data[24] 0 A9 dq[24]

sf_data[25] 0 B3 dq[25]

sf_data[26] 0 A5 dq[26]

sf_data[27] 0 A4 dq[27]

sf_data[28] 0 C10 dq[28]

sf_data[29] 0 A3 dq[29]

sf_data[30] 0 B6 dq[30]

sf_data[31] 0 A8 dq[31]

sf_addr[0] 1 B11 ctl[12]

sf_addr[1] 0 C9 ctl[11]

sf_csn 1 C12 ctl[0]

sf_wen 1 A13 ctl[1]

sf_oen 1 B12 ctl[2]

sf_rdn 8 A15 ctl[3]

sf_pktend 8 B16 ctl[7]

sf_clko 0 B9 pclk

sf_flaga 1 C11 ctl[4]

sf_flagb 1 C13 ctl[5]

Signal sysIO Bank LatticeECP3 BGA Ball

EZ-USB FX3

Interface Signal

Lattice USB3 Video Bridge Development Kit

Table 4. LatticeECP3 (U1) Bank Voltage Settings

Clock Sources

There are two crystals, two oscillators, and a programmable clock generator on the Lattice USB 3.0 Video Bridge

Development Kit. The two crystals are used as clocks for the ADV7611 and the EZ-USB FX3. One oscillator is

used to provide the 32.768 kHz RTC clock to the EZ-USB FX3, While the 27 MHz oscillator is used as the refer-

ence clock for the Si5338 clock generator, which is used to drive the (by default 100 MHz) system and GPIF inter-

face frequency to the LatticeECP3 (U1), as well as the reference differential clock to the LatticeECP3 SERDES

used for the SDI interface. Table 5 shows the oscillator usage. Locations Y2 and Y3 are the oscillators.

Table 5. LatticeECP3 (U1)

HDMI Video Input

The HDMI Video input is connected to the Analog Devices ADV7611 (U3).

The ADV7611 is an HDMI receiver that supports all mandatory 2D and 3D video formats defined in HDMI 1.4a. It

supports HDMI audio extraction and has an audio output port for the audio data extracted from the HDMI stream.

Accessible audio formats are: a stream from the I2S serializer (two audio channels), a stream from the S/PDIF seri-

alizer (two uncompressed channels or N compressed channels, for example, AC3) and DST stream.

The LatticeECP3 interfaces to the ADV7611 as shown in Table 6.

Table 6. LatticeECP3(U1) connections to ADV7611 (U3)

LatticeECP3 Bank VCCIO Voltage Comment

0 and 1 2.5 V EZ-USB FX3

2 Adjustable

Expansion connector SubLVDS, MIPI

3.3 V: Jumper on J2 pins 1-2

2.5 V: Jumper on J2 pins 3-4

1.2 V: Jumper on J2 pins 5-6

3 3.3 V Expansion connector SubLVDS, MIPI

6 3.3 V ADV7611, I2C and UART bus

7 3.3 V ADV7611

8 2.5 V LatticeECP3 programming, EZ-USB FX3

Quad A 1.2 V SERDES

Source Frequency Comment

LatticeECP3

Input and IO Setting

Y1 28.63636 MHz ADV7611 pins 58 and 59 -

Y2 27 MHz SI5338 pin 3 -

Y3 32.768 kHz CYUSB3014 pin D6 -

Y4 19.2 MHz CYUSB3014 pins C6 and C7 -

Si5338 CLK0 (A/B) Adjustable QuadA pins U10 and T10

Si5338 CLK2 (A) Adjustable (100 MHz Typ.) LatticeECP3 pin R2

Signal sysIO Bank LatticeECP3 BGA Ball ADV7611 Signal

vp[2] 7 F3 p[0]

vp[3] 7 F1 p[1]

vp[4] 7 G1 p[2]

vp[5] 7 H1 p[3]

vp[6] 7 J1 p[4]

Lattice USB3 Video Bridge Development Kit

SDI Video Input

The SDI Video input is connected to the Texas Instruments LMH0394 (U2) SDI cable equalizer. The equalizer oper-

ates over a wide range of data rates, from 125 Mbps to 2.97 Gbps and supports SMPTE 424M, SMPTE 292M,

SMPTE 344M, and SMPTE 259M standards.

The signal connections between the LatticeECP3 device and the LMH0394 are shown in Table 7.

Table 7. LatticeECP3(U1) connections to LMH0384 (U2)

vp[7] 7 H3 p[5]

vp[8] 7 G2 p[6]

vp[9] 7 L1 p[7]

vp[12] 7 G3 p[8]

vp[13] 7 J2 p[9]

vp[14] 7 K2 p[10]

vp[15] 7 J3 p[11]

vp[16] 7 H2 p[12]

vp[17] 7 L2 p[13]

vp[18] 7 N2 p[14]

vp[19] 7 N3 p[15]

vp[22] 7 M2 p[16]

vp[23] 6 R3 p[17]

vp[24] 7 N1 p[18]

vp[25] 6 T2 p[19]

vp[26] 6 V1 p[20]

vp[27] 6 T3 p[21]

vp[28] 7 L3 p[22]

vp[29] 7 M1 p[23]

hs 7 E3 hs

vs 7 D2 vs/field/alsb

de 7 E2 de

pclk 7 M3 llc

lrclk_a 7 D3 lrclk

sclk_a 7 D1 sclk/int2

i2s0_a 7 E1 ap

adv_t_rst_n 6 V2 resetn

Signal sysIO Bank Polarity LatticeECP3 BGA Ball LMH0394 signal

sdi_inp_ch0 Quad A P W14 SDO

sdi_inn_ch0 Quad A N W15 SDOn

Signal sysIO Bank LatticeECP3 BGA Ball ADV7611 Signal

Lattice USB3 Video Bridge Development Kit

Expansion Connector (J1)

Expansion connector Molex 52559-3652 is provided to connect the LatticeECP3 to a camera or a sensor. Various

camera or sensor module interfaces are supported: parallel, SubLVDS or MIPI-CSI-2. Adapter boards are available

for various camera/sensor options: HDR-60 NanoVesta connector with SubLVDS lines (MN34041), Sony FCB-

MA130 Block camera with MIPI CSI-2 interface.

The signal connections between the LatticeECP3 device and the Molex expansion connector are shown in Table 8.

Table 8. LatticeECP3(U1) Connections to Molex Expansion Connector (J1)

Configuration/Programming Header (J4)

The J4 JTAG 1x10 header is provided on the board for accessing the LatticeECP3 JTAG port. It can be used for

downloading the LatticeECP3 FPGA bitstream and reveal troubleshooting. It cannot be used for SPI Flash pro-

gramming.

Signal sysIO Bank Polarity LatticeECP3 BGA Ball Molex pin number

mipi_dck_p 3 P P17 11

mipi_dck_n 3 N P19 12

mipi_d0_p 3 P R18 13

mipi_d0_n 3 N R17 14

mipi_d1_p 3 P T17 15

mipi_d1_n 3 N T18 16

mipi_d2_p 3 P R19 17

mipi_d2_n 3 N T19 18

mipi_d3_p 3 P U18 19

mipi_d3_n 3 N U19 20

mipi_gpio0 2 - L18 31

mipi_gpio1 2 - K18 32

mipi_gpio2 3 - V18 33

mipi_gpio3 3 - V19 34

mipi_lp0_0 2 - M18 24

mipi_lp0_1 2 - M19 23

mipi_lpclk_0 2 - L19 28

mipi_lpclk_1 2 - N17 27

Pin # Description LatticeECP3 BGA Ball

Pin 1 VCC -

Pin 2 TDO B1

Pin 3 TDI C1

Pin 4 PROGRAMN C19

Pin 5 NC -

Pin 6 TMS A2

Pin 7 GND -

Pin 8 TCK B2

Pin 9 DONE E19

Pin 10 INITN C18

Indice

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