Linear Technology LTC2175-12 Manuale utente

21754312fa

LTC2175-12/

LTC2174-12/LTC2173-12

Typical applicaTion

FeaTures

applicaTions

DescripTion

12-Bit, 125Msps/105Msps/

80Msps Low Power Quad ADCs

LTC2175-12, 125Msps,

2-Tone FFT, fIN = 70MHz and 75MHz

TheLTC

2175-12/LTC2174-12/LTC2173-12are4-channel,

simultaneous sampling 12-bit A/D converters designed

for digitizing high frequency, wide dynamic range signals.

They are perfect for demanding communications applica-

tions with AC performance that includes 70.6dB SNR and

88dB spurious free dynamic range (SFDR). Ultralow jitter

of 0.15psRMS allows undersampling of IF frequencies with

excellent noise performance.

DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)

and no missing codes over temperature. The transition

noise is a low 0.3LSBRMS.

The digital outputs are serial LVDS to minimize the num-

ber of data lines. Each channel outputs two bits at a time

(2-lane mode). At lower sampling rates there is a one bit

per channel option (1-lane mode). The LVDS drivers have

optional internal termination and adjustable output levels

to ensure clean signal integrity.

The ENC+and ENC–inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL, or

CMOS inputs. An internal clock duty cycle stabilizer al-

lows high performance at full speed for a wide range of

clock duty cycles.

n4-Channel Simultaneous Sampling ADC

n70.6dB SNR

n88dB SFDR

nLow Power: 545mW/439mW/369mW Total,

136mW/110mW/92mW per Channel

nSingle 1.8V Supply

nSerial LVDS Outputs: 1 or 2 Bits per Channel

nSelectable Input Ranges: 1VP-P to 2VP-P

n800MHz Full Power Bandwidth S/H

nShutdown and Nap Modes

nSerial SPI Port for Configuration

nPin Compatible 14-Bit and 12-Bit Versions

n52-Pin (7mm ×8mm) QFN Package

nCommunications

nCellular Base Stations

nSoftware Defined Radios

nPortable Medical Imaging

nMultichannel Data Acquisition

nNondestructive Testing

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30 40 50 60

217512 TA01b

DATA

SERIALIZER

ENCODE

INPUT

SERIALIZED

LVDS

OUTPUTS

1.8V

VDD

1.8V

OVDD

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

DATA

CLOCK

OUT

FRAME

OGND

GND

217512 TA01

S/H

CHANNEL 1

ANALOG

INPUT

12-BIT

ADC CORE

S/H

CHANNEL 2

ANALOG

INPUT

12-BIT

ADC CORE

S/H

CHANNEL 3

ANALOG

INPUT

12-BIT

ADC CORE

S/H

CHANNEL 4

ANALOG

INPUT

12-BIT

ADC CORE

PLL

LTC2175-12/

LTC2174-12/LTC2173-12

21754312fa

absoluTe MaxiMuM raTings

(Notes 1, 2)

pin conFiguraTions

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2175CUKG-12#PBF LTC2175CUKG-12#TRPBF LTC2175UKG-12 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C

LTC2175IUKG-12#PBF LTC2175IUKG-12#TRPBF LTC2175UKG-12 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C

LTC2174CUKG-12#PBF LTC2174CUKG-12#TRPBF LTC2174UKG-12 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C

LTC2174IUKG-12#PBF LTC2174IUKG-12#TRPBF LTC2174UKG-12 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C

LTC2173CUKG-12#PBF LTC2173CUKG-12#TRPBF LTC2173UKG-12 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C

LTC2173IUKG-12#PBF LTC2173IUKG-12#TRPBF LTC2173UKG-12 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Supply Voltages

VDD, OVDD................................................ –0.3V to 2V

Analog Input Voltage (AIN+, AIN–,

PAR/SER, SENSE) (Note 3).......... –0.3V to (VDD + 0.2V)

Digital Input Voltage (ENC+, ENC–, CS,

SDI, SCK) (Note 4).................................... –0.3V to 3.9V

SDO (Note 4)............................................. –0.3V to 3.9V

Digital Output Voltage................ –0.3V to (OVDD + 0.3V)

Operating Temperature Range

LTC2175C, 2174C, 2173C......................... 0°C to 70°C

LTC2175I, 2174I, 2173I ........................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

1615 17 18 19

TOP VIEW

GND

UKG PACKAGE

52-LEAD (7mm ×8mm) PLASTIC QFN

20 21 22 23 24 25 26

5152 50 49 48 47 46 45 44 43 42 41

1AIN1+

AIN1–

VCM12

AIN2+

AIN2–

REFH

REFL

AIN3+

AIN3–

VCM34

AIN4+

AIN4–

OUT2A+

OUT2A–

OUT2B+

OUT2B–

DCO+

DCO–

OVDD

OGND

FR+

FR–

OUT3A+

OUT3A–

OUT3B+

OUT3B–

VDD

SENSE

GND

VREF

PAR/SER

SDO

GND

OUT1A+

OUT1A–

OUT1B+

OUT1B–

VDD

ENC+

ENC–

SCK

SDI

GND

OUT4B–

OUT4B+

OUT4A–

OUT4A+

TJMAX = 150°C, θJA = 28°C/W

EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB

21754312fa

LTC2175-12/

LTC2174-12/LTC2173-12

converTer characTerisTics

The ldenotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA= 25°C. (Note 5)

PARAMETER CONDITIONS

LTC2175-12 LTC2174-12 LTC2173-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Resolution (No Missing Codes) l12 12 12 Bits

Integral Linearity Error Differential Analog Input (Note 6) l–1 ±0.3 1 –1 ±0.3 1 –1 ±0.3 1 LSB

Differential Linearity Error Differential Analog Input l–0.4 ±0.1 0.4 –0.4 ±0.1 0.4 –0.4 ±0.1 0.4 LSB

Offset Error (Note 7) l–12 ±3 12 –12 ±3 12 –12 ±3 12 mV

Gain Error Internal Reference

External Reference

–2.8

–1.3

0.2

–2.8

–1.3

0.2

–2.8

–1.3

0.2

%FS

Offset Drift ±20 ±20 ±20 µV/°C

Full-Scale Drift Internal Reference

External Reference

±35

±25

±35

±25

±35

±25

ppm/°C

Gain Matching External Reference ±0.2 ±0.2 ±0.2 %FS

Offset Matching ±3 ±3 ±3 mV

Transition Noise External Reference 0.3 0.3 0.3 LSBRMS

analog inpuT

The ldenotes the specifications which apply over the full operating temperature range, otherwise

specifications are at TA= 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (AIN+– AIN–) 1.7V < VDD < 1.9V l1 to 2 VP-P

VIN(CM) Analog Input Common Mode (AIN++ AIN–)/2 Differential Analog Input (Note 8) lVCM – 100mV VCM VCM + 100mV V

VSENSE External Voltage Reference Applied to SENSE External Reference Mode l0.625 1.250 1.300 V

IINCM Analog Input Common Mode Current Per Pin, 125Msps

Per Pin, 105Msps

Per Pin, 80Msps

155

130

100

µA

IIN1 Analog Input Leakage Current No Encode 0 < AIN+, AIN–< VDD,l–1 1 µA

IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l–3 3 µA

IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l–6 6 µA

tAP Sample-and-Hold Acquisition Delay Time 0 ns

tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 psRMS

CMRR Analog Input Common Mode Rejection Ratio 80 dB

BW-3B Full-Power Bandwidth Figure 6 Test Circuit 800 MHz

LTC2175-12/

LTC2174-12/LTC2173-12

21754312fa

DynaMic accuracy

The ldenotes the specifications which apply over the full operating temperature range,

otherwise specifications are at TA= 25°C. AIN = –1dBFS. (Note 5)

SYMBOL PARAMETER CONDITIONS

LTC2175-12 LTC2174-12 LTC2173-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

SNR Signal-to-Noise Ratio 5MHz Input

70MHz Input

140MHz Input

69.3

70.6

70.3

69.2

70.6

70.5

70.3

69.3

70.6

70.5

70.3

dBFS

SFDR Spurious Free Dynamic Range

2nd or 3rd Harmonic

5MHz Input

70MHz Input

140MHz Input

dBFS

Spurious Free Dynamic Range

4th Harmonic or Higher

5MHz Input

70MHz Input

140MHz Input

dBFS

S/(N+D) Signal-to-Noise Plus

Distortion Ratio

5MHz Input

70MHz Input

140MHz Input

68.6

70.6

70.4

68.7

70.6

70.4

68.9

70.6

70.4

dBFS

Crosstalk, Near Channel 10MHz Input (Note 12) –90 –90 –90 dBc

Crosstalk, Far Channel 10MHz Input (Note 12) –105 –105 –105 dBc

inTernal reFerence characTerisTics

The ldenotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA= 25°C. AIN = –1dBFS. (Note 5)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V

VCM Output Temperature Drift ±25 ppm/°C

VCM Output Resistance –600µA < IOUT < 1mA 4 Ω

VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V

VREF Output Temperature Drift ±25 ppm/°C

VREF Output Resistance –400µA < IOUT < 1mA 7 Ω

VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V

21754312fa

LTC2175-12/

LTC2174-12/LTC2173-12

DigiTal inpuTs anD ouTpuTs

The ldenotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA= 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ENCODE INPUTS (ENC+, ENC–)

Differential Encode Mode (ENC–Not Tied to GND)

VID Differential Input Voltage (Note 8) l0.2 V

VICM Common Mode Input Voltage Internally Set

Externally Set (Note 8)

1.1

1.2

1.6

VIN Input Voltage Range ENC+, ENC–to GND l0.2 3.6 V

RIN Input Resistance (See Figure 10) 10 kΩ

CIN Input Capacitance 3.5 pF

Single-Ended Encode Mode (ENC–Tied to GND)

VIH High Level Input Voltage VDD = 1.8V l1.2 V

VIL Low Level Input Voltage VDD = 1.8V l0.6 V

VIN Input Voltage Range ENC+to GND l0 3.6 V

RIN Input Resistance (See Figure 11) 30 kΩ

CIN Input Capacitance 3.5 pF

DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)

VIH High Level Input Voltage VDD = 1.8V l1.3 V

VIL Low Level Input Voltage VDD = 1.8V l0.6 V

IIN Input Current VIN = 0V to 3.6V l–10 10 µA

CIN Input Capacitance 3 pF

SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)

ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω

IOH Logic High Output Leakage Current SDO = 0V to 3.6V l–10 10 µA

COUT Output Capacitance 3 pF

DIGITAL DATA OUTPUTS

VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

247

125

350

175

454

250

VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

1.125

1.250

1.375

RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω

LTC2175-12/

LTC2174-12/LTC2173-12

21754312fa

power requireMenTs

The ldenotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA= 25°C. (Note 9)

SYMBOL PARAMETER CONDITIONS

LTC2175-12 LTC2174-12 LTC2173-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

VDD Analog Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

OVDD Output Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

IVDD Analog Supply Current Sine Wave Input l276 300 218 240 180 196 mA

IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode

2-Lane Mode, 3.5mA Mode

PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode

2-Lane Mode, 3.5mA Mode

545

585

596

637

439

479

488

527

369

409

405

446

PSLEEP Sleep Mode Power 1 1 1 mW

PNAP Nap Mode Power 85 85 85 mW

PDIFFCLK Power Increase With Differential Encode Mode Enabled

(No Increase for Sleep Mode)

20 20 20 mW

TiMing characTerisTics

The ldenotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA= 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS

LTC2175-12 LTC2174-12 LTC2173-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

fSSampling Frequency (Notes 10,11) l5 125 5 105 5 80 MHz

tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

3.8

100

4.52

4.76

100

5.93

6.25

100

tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

3.8

100

4.52

4.76

100

5.93

6.25

100

tAP Sample-and-Hold

Acquisition Delay Time

0 0 0 ns

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Digital Data Outputs (RTERM = 100Ω Differential, CL= 2pF to GND on Each Output)

tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization

2-Lanes, 14-Bit Serialization

2-Lanes, 12-Bit Serialization

1-Lane, 16-Bit Serialization

1-Lane, 14-Bit Serialization

1-Lane, 12-Bit Serialization

1/(8 • fS)

1/(7 • fS)

1/(6 • fS)

1/(16 • fS)

1/(14 • fS)

1/(12 • fS)

tFRAME FR to DCO Delay (Note 8) l0.35 • tSER 0.5 • tSER 0.65 • tSER s

tDATA DATA to DCO Delay (Note 8) l0.35 • tSER 0.5 • tSER 0.65 • tSER s

tPD Propagation Delay (Note 8) l0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s

tROutput Rise Time Data, DCO, FR, 20% to 80% 0.17 ns

tFOutput Fall Time Data, DCO, FR, 20% to 80% 0.17 ns

DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P

Pipeline Latency 6 Cycles

21754312fa

LTC2175-12/

LTC2174-12/LTC2173-12

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SPI Port Timing (Note 8)

tSCK SCK Period Write Mode

Readback Mode, CSDO = 20pF, RPULLUP

= 2k

250

tSCS to SCK Setup Time l5 ns

tHSCK to CS Setup Time l5 ns

tDS SDI Setup Time l5 ns

tDH SDI Hold Time l5 ns

tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP

= 2k

l125 ns

TiMing characTerisTics

The ldenotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA= 25°C. (Note 5)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND with GND and OGND

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: When these pin voltages are taken below GND they will be

clamped by internal diodes. When these pin voltages are taken above VDD

they will not be clamped by internal diodes. This product can handle input

currents of greater than 100mA below GND without latchup.

Note 5: V

= OV

= 1.8V, f

SAMPLE

= 125MHz (LTC2175), 105MHz

(LTC2174), or 80MHz (LTC2173), 2-lane output mode, differential ENC+/

ENC–= 2V

P-P

sine wave, input range = 2V

P-P

with differential drive, unless

otherwise noted.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

best fit straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 7: Offset error is the offset voltage measured from –0.5 LSB when

the output code flickers between 0000 0000 0000 and 1111 1111 1111

in 2’s complement output mode.

Note 8: Guaranteed by design, not subject to test.

Note 9: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2175), 105MHz

(LTC2174), or 80MHz (LTC2173), 2-lane output mode, ENC+= single-

ended 1.8V square wave, ENC–= 0V, input range = 2VP-P with differential

drive, unless otherwise noted. The supply current and power dissipation

specifications are totals for the entire chip, not per channel.

Note 10: Recommended operating conditions.

Note 11: The maximum sampling frequency depends on the speed grade

of the part and also which serialization mode is used. The maximum serial

data rate is 1000Mbps so tSER must be greater than or equal to 1ns.

Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to Ch.4.

Far-channel crosstalk refers to Ch.1 to Ch.3, Ch.1 to Ch.4, Ch.2 to Ch.3, and

Ch.2 to Ch.4.

LTC2175-12/

LTC2174-12/LTC2173-12

21754312fa

2-Lane Output Mode, 14-Bit Serialization

ANALOG

INPUT

ENC–

ENC+

DCO–

DCO+

tAP

tENCH tENCL

tSER

tPD

tDATA

tFRAME

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3

N+1

N+2

217512 TD02

D5 D3 D1 DX*D11 D9 D7 D5 D3 D1 DX*D11 D9 D7 D5 D3 D1 D11 D9 D7

OUT#A–

OUT#A+

FR–

FR+

D4 D2 D0 DY*D10 D8 D6 D4 D2 D0 DY*

DX*

DY*D10 D8 D6 D4 D2 D0 D10 D8 D6

OUT#B–

OUT#B+

NOTE THAT IN THIS MODE FR+/FR–HAS TWO TIMES THE PERIOD OF ENC+/ENC–

*DXAND DYARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT

VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DXAND DYARE SET TO

LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

TiMing DiagraMs

2-Lane Output Mode, 16-Bit Serialization

ANALOG

INPUT

ENC–

ENC+

DCO–

DCO+

tAP

tENCH tENCL

tSER

tPD

tDATA

tFRAME

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4

N+1

217512 TD01

D3 D1 DX* 0 D11 D9 D7 D5 D3 D1 DX* 0 D11 D9 D7

OUT#A–

OUT#A+

FR–

FR+

D2 D0 DY* 0 D10 D8 D6 D4 D2 D0 DY* 0 D10 D8 D6

OUT#B–

OUT#B+

*DXAND DYARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT

VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DXAND DYARE SET TO

LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

21754312fa

LTC2175-12/

LTC2174-12/LTC2173-12

TiMing DiagraMs

2-Lane Output Mode, 12-Bit Serialization

1-Lane Output Mode, 16-Bit Serialization

ANALOG

INPUT

ENC–

ENC+

DCO–

DCO+

tAP

tENCH tENCL

tSER

tPD

tDATA

tFRAME

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4

N+1

217512 TD03

D7 D5 D3 D1 D11 D9 D7 D5 D3 D1 D11 D9 D7

OUT#A–

OUT#A+

FR+

FR–

D6 D4 D2 D0 D10 D8 D6 D4 D2 D0 D10 D8 D6

OUT#B–

OUT#B+

ANALOG

INPUT

ENC–

ENC+

DCO–

DCO+

tAP

tENCH tENCL

tSER

tPD

tDATA

tFRAME

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4

N+1

tSER

217512 TD05

DX* DY* DX* DY*0 0 D11 D10 D9 D8 D10 D9 D8D7 D6 D5 D4 D3 D2 D1 D0 0 0 D11

OUT#A–

OUT#A+

FR–

FR+

OUT#B+, OUT#B–ARE DISABLED

*DXAND DYARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT

VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DXAND DYARE SET TO

LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

LTC2175-12/

LTC2174-12/LTC2173-12

21754312fa

TiMing DiagraMs

One-Lane Output Mode, 14-Bit Serialization

ANALOG

INPUT

ENC–

ENC+

DCO–

DCO+

tAP

tENCH tENCL

tSER

tPD

tDATA

tFRAME

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4

N+1

tSER

217512 TD06

D1 D0 DX* DX* DY*DY*D11 D10 D9 D8 D10 D9 D8D7 D6 D5 D4 D3 D2 D1 D0 D11

OUT#A–

OUT#A+

FR–

FR+

OUT#B+, OUT#B–ARE DISABLED

*DXAND DYARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT

VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DXAND DYARE SET TO

LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

One-Lane Output Mode, 12-Bit Serialization

ANALOG

INPUT

ENC–

ENC+

DCO–

DCO+

tAP

tENCH tENCL

tSER

tPD

tDATA

tFRAME

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4

N+1

tSER

217512 TD07

D3 D2 D1 D0 D11 D10 D9 D8 D10 D9D7 D6 D5 D4 D3 D2 D1 D0 D11

OUT#A–

OUT#A+

FR–

FR+

OUT#B+, OUT#B–ARE DISABLED

tStDS

A5 A4 A3 A2 A1 A0 XX

D7 D6 D5 D4 D3 D2 D1 D0

XX XX XX XX XX XX XX

SCK

SDI R/W

SDO HIGH IMPEDANCE

tDH

tDO

tSCK tH

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

217512 TD04

SCK

SDI R/W

SDO HIGH IMPEDANCE

SPI Port Timing (Readback Mode)

SPI Port Timing (Write Mode)

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