LSI L64005 Manuale utente

Final Edition May 1998

L64005

Enhanced MPEG-2

Audio/Video Decoder

Technical Manual

This document contains proprietary information of LSI Corporation. The informa-

tion contained herein is not to be used by or disclosed to third parties without the

express written permission of an ofﬁcer of LSI Corporation.

Document DB14-000045-00, Final Revision F (May, 1998)

This document describes revisions D through F of LSI Logic Corporation’s

L64005 MPEG-2 Audio/Video Decoder and will remain the ofﬁcial reference

source for all revisions/releases of this product until rescinded by an update.

To receive product literature, call us at 1.800.574.4286 (U.S. and Canada);

+32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, and Europe)

and ask for Department JDS; or visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein

at any time without notice. LSI Logic does not assume any responsibility or lia-

bility arising out of the application or use of any product described herein, except

as expressly agreed to in writing by LSI Logic; nor does the purchase or use of

a product from LSI Logic convey a license under any patent rights, copyrights,

trademark rights, or any other of the intellectual property rights of LSI Logic or

third parties.

In particular, supply of the LSI Logic IC L64005 does not convey a license or

imply a right under certain patents and/or other industrial or intellectual property

rights claimed by IRT, CCETT and Philips, to use this IC in any ready-to-use elec-

tronic product. The purchaser is herby notiﬁed that Philips, CCETT and IRT are

of the opinion that a generally available patent license for such use is required

from them. No warranty or indemnity of any sort is provided by LSI Logic regard-

ing patent infringement.

TRADEMARK ACKNOWLEDGMENT

LSI Logic logo design is a registered trademark of LSI Logic Corporation. All

other brand and product names may be trademarks of their respective compa-

nies.

L64005 MPEG-2 Audio/Video Decoder Technical Manual iii

Preface

This book is the primary reference and technical manual for the L64005

MPEG-2 Audio/Video Decoder. It contains a complete functional descrip-

tion and includes complete physical and electrical speciﬁcations for the

L64005.

Audience This document assumes that you have some familiarity with microproces-

sors and related support devices. The people who beneﬁt from this book

are:

♦Engineers and managers who are evaluating the processor for pos-

sible use in a system

♦Engineers who are designing the processor into a system

Organization This document has the following chapters:

♦Chapter 1 Introduction, describes the system interface and the

architecture of the L64005 MPEG-2 Audio/Video Decoder.

♦Chapter 2 Registers, discusses the L64005 internal registers. It also

provides a description of the internal memory mapping and how the

registers are accessed from the system interface. This chapter is

intended primarily for system programmers who are developing soft-

ware drivers.

♦Chapter 3 Signals, provides detailed information on the L64005 sig-

nals. The signal descriptions are useful for hardware designers who

are interfacing the L64005 with other devices.

♦Chapter 4 Video Data Flow, This chapter describes the MPEG bit-

stream construction, parsing and error handling as well as the oper-

ation of the channel buffer.

iv Preface

♦Chapter 5 External Memory Interface, describes the frame mem-

ory interface.

♦Chapter 6 Video Interface and On-Screen Display, describes the

L64005 video interface and video timing characteristics.

♦Chapter 7 Audio Decoder, describes the details of the integrated

two channel Musicam (MPEG) audio decoder.

♦Chapter 8 System Stream Decoding and Synchronization,

describes the resources that the L64005 provides for parsing an

MPEG system stream.

♦Chapter 9 Speciﬁcations, speciﬁes the L64005 electrical and

mechanical characteristics.

♦Appendix A Interfacing the L64005 to 5-V Signals, describes how

to interface LSI Logic’s 3.3-V L64005 MPEG-2 Audio/Video Decoder

to 5-V signals.

♦Customer Feedback.

Publications ISO/IEC 13818,

Generic Coding of Moving Pictures and Associated

Audio

(MPEG-2), Draft International Standard

ISO/IEC Copyright Ofﬁce,

Case Postal 56, CH1211 Genève 20, Switzerland.

ISO/IEC 11172 (1993),

Information Technology—Coding of Moving Pic-

ture and Associated Audio for Digital Storage Media at up to about

1.5 Mbit/s

(MPEG-1).

L64002 MPEG-2 Audio/Video Decoder Technical Manual

, LSI Logic

Corp.

L64007 MPEG-2 Transport Demultiplexer

, LSI Logic Corp.

Conventions

Used in This

Manual

Unless otherwise speciﬁed,

MPEG

refers to the MPEG-2 standard.

MSB

indicates the most-signiﬁcant bit or byte.

LSB

indicates the least-

signiﬁcant bit or byte.The ﬁrst time a word or phrase is deﬁned in this

manual, it is

italicized.

The following signal naming conventions are used throughout this

manual:

L64005 MPEG-2 Audio/Video Decoder Technical Manual v

♦A level-signiﬁcant signal that is true or valid when the signal is LOW

always has an overbar ( ) over its name.

♦An edge-signiﬁcant signal that initiates actions on a HIGH-to-LOW

transition always has an overbar ( ) over its name.

The word

assert

means to drive a signal true or active. The word

deassert

means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the preﬁx “0x” before the num-

ber—for example, 0x32CF. Binary numbers are indicated by a sub-

scripted “2” following the number—for example, 0011.0010.1100.11112.

Revision

History This section lists the changes in this document from initial release to the

current version.

Notice for

L64002 Users This section is for customers using the L64002, and who want to upgrade

to the L64005. The following is a brief description of the pertinent

changes, with emphasis on pinout and necessary software changes.

Please note: LSI Logic recommends building new boards to

ensure L64005 to L64002 compatibility. A simple 0 Ω resis-

tor jumper (for pin 69) allows switching between the loop ﬁl-

ter and the CAS signal.

Pinout Changes If the L64005 is used with fast page mode DRAM, then a few changes

are needed. For further information, please refer to Chapter 9: Speciﬁca-

tions.

Version Release Date Comments

L64005.ADV.0 March 4, 1996 Initial release

L64005.ADV.1 August 23, 1996 Major modiﬁcations to most chapters.

Changed register map, pinout, and

signal descriptions. Added Section

6.3, “Reduced Memory Mode,” Section

3.6, “PLL Interface,” and Section 5.5,

“Channel Buffer Architecture”.

L64005.Final May 11, 1998 Minor changes to most chapters.

Added corrections from document

review and relevant items from

L64005 Rev. E and F ECNs.

vi Preface

♦Pin 64 is CAS for the L64005, not BA9 (BA9 has been removed).

♦For Rev. E and F devices Pin 69 is now not connected (NC) and no

external loop ﬁlter is required. The ﬁlter may be left in place on any

board that already has it designed in.

For the L64005 Rev. D, Pin 69 is LP2. Regardless of the DRAM

mode used, an external loop ﬁlter must be included in the design

(requires one resistor and two capacitors for an off-chip loop ﬁlter).

♦The DRAM interface now supports both regular and synchronous

DRAM modes. See Section 5.3.2, “Synchronous DRAM Mode,” for

more information on the SDRAM interface.

♦New AC timing speciﬁcations and drawings have been added to Sec-

tion 9.1

♦Pin 68 is Analog VDD (AVDD), and pin 70 is Analog GND (AGND).

These pins must be isolated from other VDD and VSS pins.

♦Please note that the L64005 has an on-chip PLL, so the 27-MHz

input clock must have low jitter (<300ps).

♦The duty cycle for SYSCLK has been speciﬁed slightly differently.

Please refer to Chapter 9, Speciﬁcations, for details.

Software

Changes A few changes must be made to L64005 supporting software.

♦Bit 0in Group 7, Register 27 must be set for reduced memory mode

(1=RMM, 0=Normal).

♦If reduced memory mode is used, Group 7, Register 27, Bits [7:2]

must be set to determine the number of 8-line segments used for a

B-frame decode.

♦Bits [4:3] of Group 7, Register 1 are no longer used for PMCT (1CAS

enable) or 512-page size select. In the L64005, bits [4:3] are used

to select the DRAM mode. Refer to Chapter 2 for more details.

♦In the L64005 32-bit mode is not supported. Bit 5 of Group 7, Reg-

ister 1 is now reserved.

♦Bit 6 of Group 7, Register 26 controls line doubling for the interlaced

display mode.

♦In the L64005, bits [7:0] in Group 7, Register 28 contains the hori-

zontal word origin of the luma and the chroma.

L64005 MPEG-2 Audio/Video Decoder Technical Manual vii

♦Additional ﬁeld status bits have been added to the register map. Odd

Field First and Last Active Field have been added to Group 6, Reg-

ister 31, Bits [3:2]. Refer to Section 2.8.18, “Group 6 Display Mode

1” for more details.

viii Preface

L64005 MPEG-2 Audio/Video Decoder Technical Manual ix

Contents

Chapter 1 Introduction

1.1 Video Compression and Decompression Concepts 1-1

1.1.1 Video Encoding 1-2

1.1.2 Bitstream Syntax 1-5

1.1.3 Video Decoding 1-7

1.2 Audio Compression and Decompression Concepts 1-8

1.2.1 MPEG Audio Encoding 1-8

1.2.2 Audio Decoding 1-11

1.3 Standards Compliance 1-11

1.3.1 MPEG-1 1-12

1.3.2 MPEG-2 1-12

1.4 Terms and Concepts 1-12

1.5 System Overview 1-17

1.5.1 Video Decoding 1-17

1.5.2 Audio Decoding 1-17

1.5.3 Post Processing 1-18

1.5.4 On-Screen Display 1-18

1.5.5 PES Decoding 1-18

1.5.6 Video Output 1-19

1.5.7 Audio Output 1-19

1.5.8 User Interface 1-19

1.5.9 Memory Utilization 1-19

1.5.10 Error Concealment 1-20

1.5.11 Mechanical and Electrical 1-20

1.6 L64005 Overview 1-20

1.6.1 MPEG-2 Video Decoder 1-20

1.6.2 System Layer Decoding 1-21

1.6.3 Video Output Features 1-21

1.6.4 On-Screen Display 1-24

1.6.5 Audio Decoder 1-24

x Contents

1.6.6 System Controller Interface 1-25

1.6.7 Channel Interface 1-27

1.6.8 Bitstream Syntax and Grammar 1-27

1.7 Features 1-28

Chapter 2 Registers

2.1 L64005 Register Overview 2-1

2.1.1 Writing a Single Register 2-14

2.1.2 Reading or Writing Multiple Registers

in a Group 2-15

2.2 Group 0 Address Indirection Register 2-15

2.3 Group 1 Status 0 Register 2-16

2.4 Group 2 Status 1 Register 2-18

2.5 Group 3 Interrupt Register 0 2-19

2.6 Group 4 Interrupt Register 1 2-21

2.7 Group 5 Control Register 2-22

2.8 Group 6 Secondary Control Registers 2-23

2.8.1 Group 6 User Data FIFO 2-23

2.8.2 Group 6 Error Status Register 2-24

2.8.3 Group 6 Forward Anchor Luma

Base Address 2-25

2.8.4 Group 6 Forward Anchor Chroma

Base Address 2-26

2.8.5 Group 6 Backward Anchor Luma

Base Address 2-26

2.8.6 Group 6 Backward Anchor Chroma

Base Address 2-27

2.8.7 Group 6 Display Luma Base Address 2-27

2.8.8 Group 6 Display Chroma Base Address 2-27

2.8.9 Group 6 VBI1 Luma Base Address 2-28

2.8.10 Group 6 VBI1 Chroma Base Address 2-28

2.8.11 Group 6 VBI2 Luma Base Address 2-29

2.8.12 Group 6 VBI2 Chroma Base Address 2-29

2.8.13 Group 6 VBI Size 2-30

2.8.14 Group 6 OSD Control Register 2-30

2.8.15 Group 6 OSD Field 1 Pointer 2-31

2.8.16 Group 6 OSD Field 2 Pointer 2-32

2.8.17 Group 6 Display Mode 0 2-32

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