Memec Virtex-II V2MB1000 Manuale utente

Virtex-II™ V2MB1000

Development Board

User’s Guide

Version 3.0

December 2002

PN# DS-MANUAL-V2MB1000

Memec Design Development Kit Owners Certificate

Thank you for purchasing your Memec Design development kit. As an owner of

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Reference Design Center, you may download reference design examples for this

particular kit, along with source code, and application notes. As more reference

designs are added, you will be notified via e-mail. Visit the Reference Design

Center today at:

http://legacy.memec.com/solutions/reference/xilinx/

Your kit serial number is:

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(Memec, Insight or Impact) or send an e-mail to:

[email protected]

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any other services provided by Memec in connection with this product, all of which are provided “as

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essential purpose of any limited remedy.

December 2,2002 i

Table of Contents

1OVERVIEW....................................................................................................................1

2THE VIRTEX-II SYSTEM BOARD...................................................................................1

2.1 VIRTEX-II SYSTEM BOARD DESCRIPTION......................................................................2

2.2 VIRTEX-II DEVICE .....................................................................................................2

2.3 DDR MEMORY .........................................................................................................3

2.4 CLOCK GENERATION .................................................................................................4

2.5 RESET CIRCUIT........................................................................................................5

2.6 USER 7-SEGMENT DISPLAY........................................................................................5

2.6.1 7-Segment Display Signal Description..................................................................6

2.7 USER LED...............................................................................................................6

2.8 USER PUSH BUTTON SWITCHES (SW5, AND SW6) ........................................................6

2.8.1 User Push Button Switch Signal Assignments.......................................................6

2.9 USER DIP SWITCH (SW2) .........................................................................................6

2.9.1 User DIP Switch Interface ...................................................................................6

2.9.2 User DIP Switch Signal Assignments...................................................................7

2.10 RS232 PORT...........................................................................................................7

2.10.1 RS232 Interface..............................................................................................7

2.10.2 RS232 Signal Descriptions ..............................................................................8

2.11 JTAG PORT ............................................................................................................8

2.11.1 Standard JTAG Connector ..............................................................................8

2.11.2 Parallel Cable IV Port......................................................................................8

2.11.3 JTAG Chain ...................................................................................................9

2.11.4 JTAG Chain Jumper Settings ..........................................................................9

2.12 SELECTMAP/SLAVE SERIAL PORT...............................................................................9

2.12.1 Slave SelectMap...........................................................................................10

2.12.2 Master SelectMap.........................................................................................10

2.13 SLAVE SERIAL PORT ...............................................................................................11

2.14 BANK I/O VOLTAGE.................................................................................................11

2.14.1 Bank I/O Voltage Jumper Settings .................................................................11

2.15 VIRTEX-II POWER DOWN MODE................................................................................12

2.16 VIRTEX-II VBAT.....................................................................................................13

2.17 ISP PROM ...........................................................................................................13

2.18 LVDS PORT..........................................................................................................14

December 2,2002 ii

2.18.1 LVDS Interface.............................................................................................14

2.18.2 LVDS Port Signal Descriptions ......................................................................17

2.18.3 Packet Over SONET Level 4 (PL4) application...............................................19

2.19 PROGRAM SWITCH (SW2) .......................................................................................20

2.20 VOLTAGE REGULATORS...........................................................................................20

2.20.1 Voltage Regulators Jumper Settings ..............................................................21

2.21 VIRTEX-II CONFIGURATION MODE SELECT..................................................................22

2.22 P160 EXPANSION MODULE SIGNAL ASSIGNMENTS.......................................................23

3DESIGN DOWNLOAD..................................................................................................25

3.1 JTAG INTERFACE...................................................................................................25

3.1.1 Configuring the Virtex-II FPGA...........................................................................25

3.1.2 Programming the XC18V04 ISP PROM..............................................................25

3.2 SLAVE SERIAL INTERFACE........................................................................................26

3.3 MASTER SELECTMAP INTERFACE ..............................................................................26

3.4 SLAVE SELECTMAP INTERFACE.................................................................................26

REVISION HISTORY............................................................................................................27

APPENDIX A –VIRTEX-II SYSTEM BOARD SCHEMATICS..................................................28

December 2,2002 iii

Figures

FIGURE 1 –VIRTEX-II SYSTEM BOARD.........................................................................................1

FIGURE 2–VIRTEX-II SYSTEM BOARD BLOCK DIAGRAM.................................................................2

FIGURE 3–DDR INTERFACE......................................................................................................3

FIGURE 4–RESET CIRCUIT........................................................................................................5

FIGURE 5-7-SEGMENT LED DISPLAY INTERFACE.........................................................................5

FIGURE 6–USER DIP SWITCH INTERFACE...................................................................................7

FIGURE 7 –RS232 INTERFACE ..................................................................................................7

FIGURE 8–J2 JTAG CONNECTOR .............................................................................................8

FIGURE 9 –JP29 PARALLEL IV PORT..........................................................................................8

FIGURE 10–VIRTEX-II SYSTEM BOARD JTAG CHAIN....................................................................9

FIGURE 11–SELECTMAP/SLAVE SERIAL CONNECTOR.................................................................10

FIGURE 12–SLAVE SELECTMAP MODE CONFIGURATION .............................................................10

FIGURE 13–MASTER SELECTMAP MODE CONFIGURATION...........................................................11

FIGURE 14–SLAVE SERIAL MODE CONFIGURATION.....................................................................11

FIGURE 15–VIRTEX-II POWER DOWN MODE..............................................................................13

FIGURE 16–ISP PROM INTERFACE.........................................................................................14

FIGURE 17–LVDS TRANSMIT PORT.........................................................................................15

FIGURE 18–LVDS RECEIVE PORT ...........................................................................................16

FIGURE 19–LVDS TRANSMIT AND RECEIVE CONTROL PORTS ......................................................16

FIGURE 20–PACKET OVER SONET LEVEL 4 (PL4) INTERFACE ...................................................20

FIGURE 21–VIRTEX-II DEVELOPMENT BOARD VOLTAGE REGULATORS ..........................................21

FIGURE 22–DOWNLOAD SETUP...............................................................................................25

December 2,2002 iv

Tables

TABLE 1 -DDR MEMORY INTERFACE SIGNAL DESCRIPTIONS ..........................................................3

TABLE 2 –VIRTEX-II DEVELOPMENT BOARD MASTER CLOCKS.........................................................4

TABLE 3 -7-SEGMENT DISPLAY SIGNAL DESCRIPTIONS ..................................................................6

TABLE 4 -USER PUSH BUTTON SWITCH SIGNAL ASSIGNMENTS .......................................................6

TABLE 5 -USER DIP SWITCH SIGNAL ASSIGNMENTS......................................................................7

TABLE 6 -RS232 SIGNAL DESCRIPTIONS.....................................................................................8

TABLE 7 -JTAG CHAIN JUMPER SETTINGS ..................................................................................9

TABLE 8 -BANK I/O VOLTAGE JUMPER SETTINGS........................................................................12

TABLE 9 -LVDS TRANSMIT PORT SIGNAL DESCRIPTIONS.............................................................17

TABLE 10 -LVDS RECEIVE PORT SIGNAL DESCRIPTIONS.............................................................18

TABLE 11-LVDS TRANSMIT CONTROL PORT SIGNAL DESCRIPTIONS..............................................19

TABLE 12-LVDS RECEIVE CONTROL PORT SIGNAL DESCRIPTIONS ...............................................19

TABLE 13 -VOLTAGE REGULATORS JUMPER SETTINGS ................................................................21

TABLE 14 -VIRTEX-II CONFIGURATION MODE SELECT..................................................................22

TABLE 15 –JX1 USER I/O CONNECTOR....................................................................................23

TABLE 16 –JX2 USER I/O CONNECTOR....................................................................................24

December 2,2002 1

1Overview

The Virtex-II V2MB1000 Development Kit provides a complete solution for developing designs

and applications based on the Xilinx Virtex-II FPGA family. The kit bundles an expandable Virtex-

II based system board with a power supply, user guide and reference designs. Also available

from Memec Design, optional P160 expansion modules enable further application specific

prototyping and testing. Xilinx ISE software and a JTAG cable are available as kit options.

The Virtex-II system board utilizes the 1-million gate Xilinx Virtex-II device (XC2V1000-4FG456C)

in the 456 fine-pitch ball grid array package. The high gate density and large number of user I/Os

allows complete system solutions to be implemented in the advanced platform FPGA. The

system board includes a 16M x 16 DDR memory, two clock sources, RS-232 port, and additional

support circuits. An LVDS interface is provided with a 16-bit transmit and 16-bit receive port plus

clock, status, and control signals for each. The board also supports the Memec Design P160

expansion module standard, allowing application specific expansion modules to be easily added.

The Virtex-II FPGA family has the advanced features needed to fit demanding, high-performance

applications. The Virtex-II Development Kit provides an excellent platform to explore these

features so that you can quickly and effectively meet your time-to-market requirements.

2The Virtex-II System Board

The Memec Design Virtex-II System Board provides the FPGA, support circuits and the P160

expansion slot for application specific add-on cards. Figure 1 shows a picture of the board and its

features.

Figure 1–Virtex-II System Board

December 2,2002 2

2.1 Virtex-II System Board Description

A high-level block diagram of theVirtex-II development board is shown in Figure 2 followed by a brief

description of each sub-section.

3.3V

Regulator

2.5V

Regulator

User

7-Segment

Display (2)

RS232

Port

JTAG Port

ISP PROM

(XC18V04)

User

Switches

User

LEDs

SlaveSerial/

SelectMap

Clock Generator

(100 & 24Mhz)

Virtex-II FPGA

XC2V1000

(FG456)

Reset

Circuit

80-Pin Connector

P160 Module

32MB

DDR SDRAM

16-bit

LVDS Interface

1.5V

Regulator

Voltage

Regulators

Figure 2–Virtex-II System Board Block Diagram

2.2 Virtex-II Device

The Virtex-II board utilizes the Xilinx Virtex-II XC2V1000-4FG456C. The Virtex-II family is a

platform FPGA developed for high performance, low to high-density designs utilizing IP cores and

customized modules. The Virtex-II family delivers complete solutions for telecommunication,

wireless, networking, video, and DSP applications. The performance and density of the Virtex-II

family along with its supported I/O standards such as LVDS, PCI, and DDR enables FPGA

designers to meet the design requirements of the next generation Networking and

telecommunication applications. The Xilinx Virtex-II FPGA along with its supporting I/O devices

on this development board, will assist FPGA designers to prototype high-performance memory

and I/O interfaces such as complete high-performance Packet Over SONET Level 4 (PL4) over a

16-bit LVDS bus, high speed DDR memory interface, and a variety of other I/O interfaces via the

on-board I/O module.

December 2,2002 3

2.3 DDR Memory

The Virtex-II development board provides 32MB of DDR memory on the system board. This

memory is implemented using the Micron MT46V16M16TG-75 16Mx16 DDR device. A high-level

block diagram of the DDR interface is shown below followed by a table describing the DDR

memory interface signals.

Virtex-II

FPGA 16M x 16 DDR

(MT46V16M16TG-75)

Addr[12:0]

Data[15:0]

BS[1:0]

LDM

UDM

LDQS

UDQS

CSn

RASn

CASn

WEn

CLK

CLKn

CLKE

OSC

100Mhz clk_in

clk_fb

reset

Figure 3–DDR Interface

Table 1-DDR Memory Interface Signal Descriptions

Signal Name Description FPGA Pin # DDR Pin #

A0 Address 0 B18 29

A1 Address 1 A18 30

A2 Address 2 B17 31

A3 Address 3 A17 32

A4 Address 4 N17 35

A5 Address 5 P18 36

A6 Address 6 P17 37

A7 Address 7 M18 38

A8 Address 8 M19 39

A9 Address 9 M20 40

A10 Address 10 A19 28

A11 Address 11 N18 41

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