Mesa 5i25 Manuale utente

5I25

ANYTHING I/O

MANUAL

Version 1.10

This page intentionally not blank

iii

Table of Contents

GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

HARDWARE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

GENERAL .................................................... 2

BREAKOUT POWER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5V I/O TOLERANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

PRECONFIG PULL-UP ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

PCI BUS ISOLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS . . . . . . . . 4

5I25 I/O CONNECTOR PIN-OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

JTAG CONNECTOR PIN-OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

FPGA ........................................................ 8

FPGA PINOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PCI ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

EEPROM LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

BITFILE FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

NMFLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MESAFLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SPI INTERFACE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

FREE EEPROM SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

FALLBACK INDICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

FAILURE TO CONFIGURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CLOCK SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

LEDS ....................................................... 15

PULLUP RESISTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

I/O LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

STARTUP I/O VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

INTERFACE CABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

BREAKOUT POWER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PLUG AND GO KITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table of Contents

SUPPLIED CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

HOSTMOT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7I76X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7I76_7I74 .................................................... 17

G540X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7I77X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7I77_7I76 .................................................... 17

7I77_7I74 .................................................... 18

7I74X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7I78X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PROB_RFX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PIN FILES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REFERENCE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5I25 1

GENERAL

DESCRIPTION

The MESA 5I25 SuperPort is a low cost, general purpose programmable I/O card

for the PCI bus. The 5I25 is a low profile PCI card and is available with standard or low

profile brackets. The 5I25 uses standard parallel port pinouts and connectors for

compatibilitywithmostparallelportinterfacedmotioncontrol/CNCbreakoutcards,allowing

a motion control performance boost while retaining a reliable real time PCI interface.

The 5I25 is a universal PCI card so will work in 5V and 3.3V systems. The 5I25

provides 34 I/O bits (17 per connector). All I/O bits have bus switches that provide 5V

tolerance and also have the benefit of disconnecting all I/O pins when the host CPU is off,

preventing damage to the 5I25 if power is supplied to I/O pins when the host is powered

down. All I/O pins have pull-up resistors, so have a defined state at power up. Unlike the

parallelportthatthe5I25replaces,eachI/Obithasindividuallyprogrammabledirectionand

function.

A power source option allows the 5I25 to supply 5V power to breakout boards if

desired. This 5V power is protected by a per connector PTC.

Configurations are provided for hardware step generation (to MHz rates), encoder

counting, PWM, digital I/O, analog I/O, and Smart Serial remote I/O.Configurations are

available that are compatible with common breakout cards and multi axis step drives like

the Probotix-RF and the Gecko G540.

There are currently five 5I25 compatible breakout cards available from Mesa, the

7I74 through 7I78.

The7I74isaeightchannelRS-422interfacenormallyusedwithMesa’sSmartSerial

remote I/O expansion cards. The 7I75 is a simple breakout/protection card that gives direct

bidirectional access to all FPGA pins. The 7I76 is a step/dir oriented breakout with 5 axis

of buffered step/dir outputs, one spindle encoder input, one isolated 0-10V analog spindle

speed plus isolated direction and enable outputs, one RS-422 expansion port, 32 isolated

5-32V inputs and 16 isolated 5-32V 300 mA outputs. The 7I77 is a analog servo interface

with 6 encoder inputs, 6 analog +-10V outputs, one RS-422 expansion port, 32 isolated

5-32Vinputs,and16isolated5-32V300mA outputs.The5I25 supportstwobreakoutcards

so for example a 10 Axis step/dir configuration or 12 axis analog servo configuration is

possible with a single 5I25 and two Mesa breakout cards. The 7I78 is a simple 4 axis

bufferedstep/dirinterfacewithisolatedanalogspindlecontrolandspindleencoderinterface

plus one RS-422 port for I/O expansion.

5I25 2

HARDWARE CONFIGURATION

GENERAL

Hardwaresetupjumperpositionsassumethatthe5I25cardisorientedinanupright

position, that is, with the PCI connector towards the person doing the configuration.

BREAKOUT POWER OPTION

The5I25 has the option to supply 5V power from the host computer to the breakout

board. This option is used by all Mesa breakout boards to simplify wiring. The option uses

4 parallel cable signals that are normally used as grounds for supplying 5V to the remote

breakout board (DB25 pins 22,23,24 and 25). These pins are AC bypassed on both the

5I25 and Mesa breakout cards so do not compromise AC signal integrity.

The 5V power option is individually selectable for the two I/O connectors. The

breakout 5V power is protected by per connector PTC devices so will not cause damage

to the 5I25 or system if accidentally shorted. This option should only be enabled for Mesa

breakout boards or boards specifically wired to accept 5V power on DB25 pins 22 through

25. When the option is disabled DB25 pins 22 through 25 are grounded

W1 (P2 POWER ) W2 (P3 POWER)

UP UP BREAKOUT POWER ENABLED

DOWN, DOWN BREAKOUT POWER DISABLED (DEFAULT)

5V I/O TOLERANCE

The FPGA used on the 5I25 has a 4V absolute maximum input voltage

specification. To allowinterfacing with 5V inputs, the 5I25 has bus switches on all I/O pins.

The bus switches work by turning off when the input voltage exceeds a preset threshold.

The 5V I/O tolerance option is the default and should normally be left enabled.

For high speed applications where only 3.3V maximum signals are present and

overshoot clamping is desired, the 5V I/O tolerance option can be disabled. W3 controls

the 5V I/O tolerance option. When W3 is on the default UP position, 5V tolerance mode

is enabled. When W3 is in the DOWN position, 5V tolerance mode is disabled. Note that

W3 controls 5V tolerance on both P2 and P3 I/O connectors.

W3 also selects the pull-up resistor voltage, When 5V I/O tolerance mode is

selected, the I/O pull-up resistors are powered from 5V. When 5V I/O tolerance mode is

disabled, the I/O pull-up resistors are powered with 3.3V.

5I25 3

HARDWARE CONFIGURATION

PRECONFIG PULLUP ENABLE

The Xilinx FPGA on the 5I25 has the option of having weak pull-ups on all I/O pins

at power-up or reset. The default is to enable the pull-ups. To enable the built-in pull-ups,

(the default condition) jumper W4 should be placed in the UP position. To disable the

internal pull-ups, W4 should be in the DOWN position.

PCI BUS ISOLATION

The 5I25 uses bus switches to provide 5V tolerance on the PCI bus. These bus

switches can be turned off to disconnect the FPGA from the PCI bus. This is valuable

when debugging FPGA PCI firmware. W5 controls the PCI bus isolate function. For

normal operation W5 must be in the UP position. To disconnect the FPGA from the BUS,

move W5 to the DOWN position.

5I25 4

CONNECTORS

CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS

5I25 5

CONNECTORS

I/O CONNECTORS

The5I25has2I/Oconnectors,theprimaryDB25FconnectorP3andthesecondary

26 pin header connector P2, please see the 5I25IO.PIN file on the 5I25 distribution disk.

5I25 IO connector pinouts are as follows:

P3 BACK PANEL DB25F CONNECTOR PINOUT

DB25 PIN FUNCTION DB25 PIN FUNCTION

1 IO0 14 IO1

2 IO2 15 IO3

3 IO4 16 IO5

4 IO6 17 IO7

5 IO8 18 GND

6 IO9 19 GND

7 IO10 20 GND

8 IO11 21 GND

9 IO12 22 GND or 5V

10 IO13 23 GND or 5V

11 IO14 24 GND or 5V

12 IO15 25 GND or 5V

13 IO16

5I25 6

CONNECTORS

I/O CONNECTORS

P2 INTERNAL HDR26 CONNECTOR PINOUT

HDR PIN FUNCTION HDR PIN FUNCTION

1 IO17 2 IO18

3 IO19 4 IO20

5 IO21 6 IO22

7 IO23 8 IO24

9 IO25 10 GND

11 IO26 12 GND

13 IO27 14 GND

15 IO28 16 GND

17 IO29 18 GND or 5V

19 IO30 20 GND or 5V

21 IO31 22 GND or 5V

23 IO32 24 GND or 5V

25 IO33 26 GND or 5V

Note: 26 pin header P2 will match standard parallel port pin-out if terminated with

flat cable 26 pin receptacle/DB25F cable with pin1s connected (and header pin 26 left

open)

A cable/bracket hardware kit is available from MESA for the second port.

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