Microchip Technology DsPIC30F Manuale di riferimento

Page 1

Digital Signal Controller

Introduction to the dsPIC30F

Architecture (Part 1 of 2)

Microchip Technology Inc.

Welcome to the second dsPIC30F web seminar: Introduction to the

dsPIC30F Architecture, Part 1. The focus in today’s seminar will be on

the basics of the Central Processing Unit, or CPU, architecture, and the

DSP elements of the dsPIC30F architecture.

Page 2

dsPIC30F CPU Architecture

Overview

Let us begin by taking a closer look at the dsPIC30F CPU architecture.

Page 3

Architecture Highlights

lSingle CPU integrating MCU & DSP functions

lModified Harvard Bus Architecture:

l3 operand instructions: A = B + C

lExtensive Addressing Modes

l16 x 16-bit general purpose register set

lFast, deterministic interrupt response

lFlexible software Stack with overflow detection

The dsPIC30F Central Processing Unit, or CPU, seamlessly integrates the best

features of a 16-bit MCU and DSP. Single instruction thread execution simplifies

application debug and ensures deterministic operation.

The dsPIC30F architecture is a modified Harvard Bus Architecture. This means that

the program and data memories are accessed by separate buses. However, there

are mechanisms to store and access constant data from the program memory

space. This enables more efficient use of the available on-chip memory for some

applications. Some instructions, specifically the dual-operand DSP instructions,

allow dual accesses from the data RAM during the same instruction cycle. This is of

tremendous benefit for DSP applications such as signal filtering.

The dsPIC30F provides a large number of addressing modes to ease code

development and enhance C compiler efficiency. Most addressing modes operate

orthogonally on a set of sixteen 16-bit general purpose registers, which means that

by and large, all instructions support all addressing modes.

Up to 45 individually vectored interrupt sources may be programmed to one of seven

priority levels. Fixed five cycle latency, from Interrupt Request to Interrupt Service

Routine entry, provides fast, deterministic application operation. The interrupt stack

is part of the on-chip RAM, and provides automatic bound checking to prevent

underflow or overflow.

Page 4

Basic Programmer’s Model

W Registers

General Purpose

Data Registers

Address Pointers

Stack Pointer

DSP OPERAND

Registers

DSP ADDRESS

Registers

DSP Accumulators

(40-bit)

ACCA

ACCB

Program Counter

(23-bit)

Status Register

W10

W11

W12

W13

W14

W15

DSP

Status

MCU

Status

15 0

01516313239

The basic programmer’s model of the dsPIC30F is shown here.

The dsPIC30F contains sixteen 16-bit general purpose working

registers W0 through W15, which are collectively known as W registers.

These registers may be used by the programmer for storing data or

they may be used as address pointers. Moreover, the W registers are

both byte and word accessible.

Some of the W registers, besides being usable as general purpose

registers, have some special functionality. For example, W15 is

designated as the Stack Pointer to support interrupts or subroutine

calls. W4 through W13 have some special roles to play when executing

the MAC instruction. Some of the W registers are shadowed to provide

a mechanism for fast context switching, for example, in a Real Time

Operating System.

Two 40-bit accumulators are provided primarily to support DSP

operations, but could be just as useful for general-purpose MCU

applications.

The 23-bit program counter can linearly address up to 4 million

instructions.

Lastly, a 16-bit status register provides feedback on the state of the

CPU, based on the result of various MCU and DSP operations.

Page 5

Program Memory Organization*

Reset Vector-

GOTO instruction

User Flash

Program Memory

(~48K Instructions)

Configuration

Memory Space

0x000100

0x00007E

0x017FFE

0x800000

0xFFFFFE

0x000000

Interrupt Vector Table

(0x000004 -0x00007E)

Program Instructions

(0x000100 -0x017FFE)

Configuration Memory

Executable code starts at 0x100

Alternate

Vector Table

0x018000

0x7FF000

Data EEPROM

(4 K Bytes)

0x000084

0x0000FE

Reserved

Interrupt

Vector Table

Reserved

0x000002

* Sample Program

Memory Map shown

here for dsPIC30F6014

device

0x000004

The Program Memory map of the dsPIC30F includes the reset vector, interrupt

vector table, an alternate vector table, user Program Flash memory, Data

EEPROM and configuration memory space.

The Reset Vector is a 2 word GOTO instruction, and is therefore the only vector

that occupies two words. All interrupt vector locations are filled with their

respective interrupt service routine or ISR addresses, if an ISRis defined. There is

an alternate vector table that can optionally be enabled by theuser. It provides a

complete set of all interrupt vectors, and is a useful aid during system debug.

The executable 24-bit wide Program Flash memory starts at hex 100 in all

dsPIC30F devices and progresses linearly through the program address space.

The 16-bit wide Data EEPROM block resides in the upper end of the user

program memory space, and is accessible using table instructions or a feature

called Program Space Visibility. The Data EEPROM can be used for storing

application constants and other parametric data such as lookup tables and sensor

calibration constants.

Finally, the Program Memory map includes configuration memory space, which

can only be accessed using the table instructions. The Device Configuration

Registers, which are used to configure basic parameters of device operation such

as system clock source, are located in this address space.

The sample program memory map shown above is for the dsPIC30F6014 device

and will, of course, vary from one device to another.

Note that unlike PIC®MCU architectures, paging of program memory is not

required with the dsPIC30F.

Page 6

Data Memory Organization

lLinear Data Memory

l64 KB of addressable data space

lData memory is word and byte-addressable

l16-bit native data word

lData is arranged in the little-endian format

lLower (Even) address stores LS byte

lHigher (Odd) address stores MS byte

F2 34

0x10000x1001

The 64K byte of addressable linear data space contains all Special

Function Registers and Data RAM. However, unlike the PIC18F family

which featured a banked data memory using a register to select the

required bank, the dsPIC30F family has a linear data memory space. It

is both word and byte addressable by most instructions, although the

native data width is 16-bits.

The data is organized in Little-Endian format. That is, the Least

Significant byte of a word is always held at the lower address within the

word. For example, a data value hex F234 stored at location hex 1000

in data space will contain hex 34 at byte address hex 1000 and hex F2

at byte address hex 1001.

Page 7

SFR Space

0x07FF 0x07FE

2 KB

SFR Space

Data Memory Map -Example*

8 KB

SRAM Space

0x0801 0x0800

X Data Space

implemented as

SRAM

8 KB

“Near”Data Memory

Addressable directly

0x1FFE

0x1FFF

0xFFFF

Unimplemented

X Data Space

0xFFFE

Optionally used by

mapping address

range into

Program Space

via PSV mechanism

0x8001 0x8000

0x27FF 0x27FE

0x0001 0x0000

MS Byte

Address

LS Byte

Address

16-bits

* Sample Data Memory

Map shown here for

dsPIC30F6014 device

A sample dsPIC30F6014 device Data Memory map is shown here.

The physical end address of RAM is hex27FF for this device. The

memory is depicted here with each word containing 16 bits. As

mentioned earlier, each byte in the dsPIC30F data space has a unique

address. Hence, two addresses are shown for each word-the even

address for the least significant byte and the odd address for the most

significant byte.

All Special Function Registers, or SFRs, are located between the

addresses hex0000 and hex07FF.

The 8 Kilo Bytes of General-Purpose SRAM starts at address hex0800.

This RAM is viewed as one linear X-space by MCU instructions as well

as non-MAC DSP instructions.

Addresses that lie in the first 8 Kilo Bytes of addressable data space

may be directly addressed by an instruction. This range of memory

addresses is known as the Near Data Space. The Near Data Space

includes the entire range of Special Function Register addresses and

ends at address hex1FFF.

Addresses beyond hex8000 can be mapped into Program Space using

a mechanism known as Program Space Visibility (PSV).

Unlike PIC®MCU devices, the dsPIC30F does not require any banking

of data memory.

Page 8

8 KB

SRAM Space

DSC-MAC Instructions View of

Data Memory Map -Example*

X Data Space

( SRAM )

0x0801 0x0800

0x17FE0x17FF

0x1801 0x1800

Y Data Space

( SRAM )

SFR Space

0x07FF 0x07FE

2 KB

SFR Space

0x27FF 0x27FE

0x0001 0x0000

MS Byte

Address

LS Byte

Address

16-bits

* Sample Data Memory

Map shown here for

dsPIC30F6014 device

0xFFFF

Unimplemented

X Data Space

0xFFFE

Optionally used by

mapping address

range into

Program Space

via PSV mechanism

0x8001 0x8000

There are some key differences between the addressing modes

supported by MAC-class instructions and those supported by all other

instructions. The MAC class of DSP instructions have the characteristic

that they operate on 2 source operands and can simultaneously

prefetch 2 words of data from RAM. A sample dsPIC30F6014 Data

Memory map is shown here as seen by MAC-class instructions.

The RAM is viewed as split X and Y data spaces for MAC-class DSP

instructions. In most devices, X and Y RAM are equal in size. This

partitioned view of the data space enables the MAC class of instructions

to perform simultaneous dual data fetch operations from memory, using

two independent data buses for X and Y RAM.

This partitioning of X and Y RAM is not user-configurable, but varies

from one device to another.

Page 9

Instruction Set Overview

l84 instructions (including DSC)

lNearly all are one word (24 bits)

lFour are two words

lMost instructions execute in 1 Cycle, except:

lProgram Flow Changes (2 cycles)

lTABLE instructions (2 cycles)

lDouble Move Instructions (2 cycles)

lDO instruction (2 cycles)

lDivide instruction (18 cycles)

lThree operand instructions

lA = B op C

lBoosts code efficiency (assembly or C)

Let us now discuss the instruction set supported by the dsPIC30F

architecture.

The dsPIC30F CPU consists of 84 different instructions. If one

considers the various addressing modes possible, there are nearly 250

possible opcodes. Most of the instructions can be programmed inone

instruction word. However 4 instructions require an additional instruction

word; these are instructions such as Goto that involve specifying a 24-

bit program memory address.

Most instructions execute in one instruction cycle. The exceptions are

program flow changes, table instructions, double-word data moves, and

DO instructions which execute in two cycles. The divide instruction is

actually a single-cycle iterative instruction that needs to be repeated 18

times; the divide loop can be interrupted, however.

As noted earlier, the 24-bit instruction word enables three operand

instructions. This allows two source operands to be operated on, with

the result stored in a third location. This maximizes code efficiency in

both assembly and C language.

Page 10

Instruction Groups

lMOVE instructions

lMATH instructions

lLOGIC instructions

lROTATE / SHIFT instructions

lBIT Manipulation instructions

lCOMPARE / SKIP instructions

lPROGRAM FLOW instructions

lSHADOW / STACK instructions

lCONTROL instructions

lDSC instructions

The instruction set may be divided into different classes:

In general, Move instructions transfer data between Data RAM, special function registers or SFR’s, and the

W registers. Constants stored in Program Flash Memory or Data EEPROM can also be accessed using

special Table instructions. Note that all instructions manipulating data can operate on either byte or word

data.

Math instructions include addition, subtraction, multiplication, and division. Both integer and fractional

multiplication and division are supported.

Logic instructions include all common Boolean operations such as And, inclusive and exclusive Or, set,

clear, complement, and negate.

Rotate and Shift instructions include both left and right arithmetic and logical data shifts, as well as left and

right rotation of data with and without carry. The barrel shifter can shift data up to 16 bits left or right in a

single instruction cycle.

A rich set of Bit Manipulation instructions enable efficient execution of control operations. Individual data

bits can be set, cleared, toggled, tested, and copied. In addition, Find First One from Left or Right

instructions facilitate quick data searches by scanning a data word for the first non-zero bit. Another

instruction, Find First Bit Change from Left, scans a word for the first bit that differs from the sign bit.

Stack operations include Push and Pop instructions. C compilers can effectively use the W14 register as a

Frame Pointer in conjunction with the Link and Unlink instructions, to pass parameters during subroutine

calls.

Program Flow instructions include Branches, Goto, Calls, and Returns. Special registers allow Do and

Repeat loops to operate with zero overhead. Conditional execution is supported by Bit Test and Skip

instructions and Compare and Skip instructions.

Control instructions support special operations such as clearing the Watch Dog Timer, disabling interrupts

for a certain period, entering the low power operation modes, or resetting the device.

Finally, the DSP instructions provide support for a wide range of signal processing oriented operations

such as signed and unsigned multiply and MAC, square, and Euclidean distance.

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