Mips Technologies MIPS32 M14K Manuale utente

Document Number: MD00668

Revision 02.04

March 24, 2014

MIPS32® M14K™ Processor Core Family

Software User’s Manual

Unpublished rights (if any) reserved under the copyright laws of the United States of America and other countries.

This document contains information that is proprietary to MIPS Tech, LLC, a Wave Computing company (“MIPS”) and MIPS’

affiliates as applicable. Any copying, reproducing, modifying or use of this information (in whole or in part) that is not expressly

permitted in writing by MIPS or MIPS’ affiliates as applicable or an authorized third party is strictly prohibited. At a minimum,

this information is protected under unfair competition and copyright laws. Violations thereof may result in criminal penalties

and fines. Any document provided in source format (i.e., in a modifiable form such as in FrameMaker or Microsoft Word

format) is subject to use and distribution restrictions that are independent of and supplemental to any and all confidentiality

restrictions. UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD

PARTY IN SOURCE FORMAT WITHOUT THE EXPRESS WRITTEN PERMISSION OF MIPS (AND MIPS’ AFFILIATES AS APPLICABLE)

reserve the right to change the information contained in this document to improve function, design or otherwise.

MIPS and MIPS’ affiliates do not assume any liability arising out of the application or use of this information, or of any error or

omission in such information. Any warranties, whether express, statutory, implied or otherwise, including but not limited to the

implied warranties of merchantability or fitness for a particular purpose, are excluded. Except as expressly provided in any

written license agreement from MIPS or an authorized third party, the furnishing of this document does not give recipient any

license to any intellectual property rights, including any patent rights, that cover the information in this document.

The information contained in this document shall not be exported, reexported, transferred, or released, directly or indirectly, in

violation of the law of any country or international law, regulation, treaty, Executive Order, statute, amendments or

supplements thereto. Should a conflict arise regarding the export, reexport, transfer, or release of the information contained in

this document, the laws of the United States of America shall be the governing law.

The information contained in this document constitutes one or more of the following: commercial computer software,

commercial computer software documentation or other commercial items. If the user of this information, or any related

documentation of any kind, including related technical data or manuals, is an agency, department, or other entity of the United

States government ("Government"), the use, duplication, reproduction, release, modification, disclosure, or transfer of this

information, or any related documentation of any kind, is restricted in accordance with Federal Acquisition Regulation 12.212

for civilian agencies and Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of this

information by the Government is further restricted in accordance with the terms of the license agreement(s) and/or applicable

contract terms and conditions covering this information from MIPS Technologies or an authorized third party.

MIPS, MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPSr3, MIPS32, MIPS64, microMIPS32, microMIPS64, MIPS-3D, MIPS16,

MIPS16e, MIPS-Based, MIPSsim, MIPSpro, MIPS-VERIFIED, Aptiv logo, microAptiv logo, interAptiv logo, microMIPS logo, MIPS

Technologies logo, MIPS-VERIFIED logo, proAptiv logo, 4K, 4Kc, 4Km, 4Kp, 4KE, 4KEc, 4KEm, 4KEp, 4KS, 4KSc, 4KSd, M4K, M14K,

5K, 5Kc, 5Kf, 24K, 24Kc, 24Kf, 24KE, 24KEc, 24KEf, 34K, 34Kc, 34Kf, 74K, 74Kc, 74Kf, 1004K, 1004Kc, 1004Kf, 1074K, 1074Kc,

1074Kf, R3000, R4000, R5000, Aptiv, ASMACRO, Atlas, "At the core of the user experience.", BusBridge, Bus Navigator, CLAM,

CorExtend, CoreFPGA, CoreLV, EC, FPGA View, FS2, FS2 FIRST SILICON SOLUTIONS logo, FS2 NAVIGATOR, HyperDebug,

HyperJTAG, IASim, iFlowtrace, interAptiv, JALGO, Logic Navigator, Malta, MDMX, MED, MGB, microAptiv, microMIPS, Navigator,

OCI, PDtrace, the Pipeline, proAptiv, Pro Series, SEAD-3, SmartMIPS, SOC-it, and YAMON are trademarks or registered

trademarks of MIPS and MIPS’ affiliates as applicable in the United States and other countries.

All other trademarks referred to herein are the property of their respective owners.

D/W^ϯϮΠ Dϭϰ<Ρ WƌŽĐĞƐƐŽƌ ŽƌĞ &ĂŵŝůǇ ^ŽĨƚǁĂƌĞ hƐĞƌƐ DĂŶƵĂů ZĞǀŝƐŝŽŶ ϬϮϬϰ

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 3

4 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 1

Table of Contents

Chapter 1: Introduction to the MIPS32® M14K™ Processor Core.....................................................4

1.1: Features ......................................................................................................................................................4

1.2: M14K™ Core Block Diagram ......................................................................................................................8

1.2.1: Required Logic Blocks .......................................................................................................................9

1.2.1.1: Execution Unit ..........................................................................................................................9

1.2.1.2: General Purposed Register (GPR) Shadow Registers........................................................... 10

1.2.1.3: Multiply/Divide Unit (MDU) .....................................................................................................10

1.2.1.4: System Control Coprocessor (CP0) .......................................................................................10

1.2.1.5: Memory Management Unit (MMU) ......................................................................................... 12

1.2.1.6: SRAM Interface Controller...................................................................................................... 14

1.2.1.7: Power Management ...............................................................................................................15

1.2.2: Optional Logic Blocks....................................................................................................................... 16

1.2.2.1: Reference Design...................................................................................................................16

1.2.2.2: microMIPS™ ISA.................................................................................................................... 17

1.2.2.3: Memory Protection Unit.......................................................................................................... 17

1.2.2.4: Coprocessor 2 Interface .........................................................................................................17

1.2.2.5: CorExtend® User-defined Instruction Extensions..................................................................18

1.2.2.6: EJTAG Debug Support...........................................................................................................18

Chapter 2: Pipeline of the M14K™ Core.............................................................................................22

2.1: Pipeline Stages..........................................................................................................................................22

2.1.1: I Stage: Instruction Fetch.................................................................................................................24

2.1.2: E Stage: Execution...........................................................................................................................24

2.1.3: M Stage: Memory Fetch...................................................................................................................24

2.1.4: A Stage: Align ..................................................................................................................................25

2.1.5: W Stage: Writeback .........................................................................................................................25

2.2: Multiply/Divide Operations......................................................................................................................... 25

2.3: MDU Pipeline - High-performance MDU ...................................................................................................25

2.3.1: 32x16 Multiply (High-Performance MDU) ........................................................................................28

2.3.2: 32x32 Multiply (High-Performance MDU) ........................................................................................29

2.3.3: Divide (High-Performance MDU) .....................................................................................................29

2.4: MDU Pipeline - Area-Efficient MDU...........................................................................................................30

2.4.1: Multiply (Area-Efficient MDU)...........................................................................................................31

2.4.2: Multiply Accumulate (Area-Efficient MDU)....................................................................................... 32

2.4.3: Divide (Area-Efficient MDU)............................................................................................................. 32

2.5: Branch Delay.............................................................................................................................................32

2.6: Data Bypassing .........................................................................................................................................33

2.6.1: Load Delay.......................................................................................................................................34

2.6.2: Move from HI/LO and CP0 Delay..................................................................................................... 35

2.7: Coprocessor 2 Instructions........................................................................................................................ 35

2.8: Interlock Handling...................................................................................................................................... 36

2.9: Slip Conditions...........................................................................................................................................37

2.10: Instruction Interlocks................................................................................................................................38

2.11: Hazards................................................................................................................................................... 39

2.11.1: Types of Hazards...........................................................................................................................39

2.11.2: Instruction Listing...........................................................................................................................40

2.11.2.1: Instruction Encoding.............................................................................................................41

2 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04

2.11.3: Eliminating Hazards.......................................................................................................................41

Chapter 3: Memory Management of the M14K™ Core......................................................................43

3.1: Introduction................................................................................................................................................ 43

3.1.1: Memory Management Unit (MMU) ..................................................................................................43

3.1.1.1: Fixed Mapping Translation (FMT) ..........................................................................................43

3.2: Modes of Operation...................................................................................................................................44

3.2.1: Virtual Memory Segments................................................................................................................44

3.2.1.1: Unmapped Segments.............................................................................................................45

3.2.1.2: Mapped Segments .................................................................................................................46

3.2.2: User Mode........................................................................................................................................46

3.2.3: Kernel Mode.....................................................................................................................................47

3.2.3.1: Kernel Mode, User Space (kuseg) .........................................................................................49

3.2.3.2: Kernel Mode, Kernel Space 0 (kseg0)....................................................................................49

3.2.3.3: Kernel Mode, Kernel Space 1 (kseg1)....................................................................................49

3.2.3.4: Kernel Mode, Kernel Space 2 (kseg2)....................................................................................49

3.2.3.5: Kernel Mode, Kernel Space 3 (kseg3)....................................................................................49

3.2.4: Debug Mode.....................................................................................................................................49

3.2.4.1: Conditions and Behavior for Access to drseg, EJTAG Registers...........................................50

3.2.4.2: Conditions and Behavior for Access to dmseg, EJTAG Memory ........................................... 51

3.3: Fixed Mapping MMU .................................................................................................................................51

3.4: System Control Coprocessor.....................................................................................................................53

Chapter 4: Exceptions and Interrupts in the M14K™ Core...............................................................55

4.1: Exception Conditions................................................................................................................................. 55

4.2: Exception Priority.......................................................................................................................................56

4.3: Interrupts ...................................................................................................................................................57

4.3.1: Interrupt Modes................................................................................................................................57

4.3.1.1: Interrupt Compatibility Mode................................................................................................... 58

4.3.1.2: Vectored Interrupt (VI) Mode.................................................................................................. 60

4.3.1.3: External Interrupt Controller Mode .........................................................................................63

4.3.2: Generation of Exception Vector Offsets for Vectored Interrupts...................................................... 66

4.3.3: MCU ASE Enhancement for Interrupt Handling...............................................................................67

4.3.3.1: Interrupt Delivery ....................................................................................................................67

4.3.3.2: Interrupt Latency Reduction ...................................................................................................67

4.4: GPR Shadow Registers.............................................................................................................................68

4.5: Exception Vector Locations.......................................................................................................................69

4.6: General Exception Processing.................................................................................................................. 71

4.7: Debug Exception Processing ....................................................................................................................73

4.8: Exception Descriptions..............................................................................................................................74

4.8.1: Reset/SoftReset Exception..............................................................................................................74

4.8.2: Debug Single Step Exception ..........................................................................................................75

4.8.3: Debug Interrupt Exception ...............................................................................................................76

4.8.4: Non-Maskable Interrupt (NMI) Exception.........................................................................................76

4.8.5: Interrupt Exception...........................................................................................................................77

4.8.6: Debug Instruction Break Exception..................................................................................................77

4.8.7: Address Error Exception — Instruction Fetch/Data Access.............................................................77

4.8.8: SRAM Parity Error Exception...........................................................................................................78

4.8.9: Bus Error Exception — Instruction Fetch or Data Access................................................................ 78

4.8.10: Protection Exception......................................................................................................................79

4.8.11: Debug Software Breakpoint Exception ..........................................................................................79

4.8.12: Execution Exception — System Call..............................................................................................79

4.8.13: Execution Exception — Breakpoint................................................................................................80

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 3

4.8.14: Execution Exception — Reserved Instruction................................................................................ 80

4.8.15: Execution Exception — Coprocessor Unusable ............................................................................80

4.8.16: Execution Exception — CorExtend Unusable................................................................................81

4.8.17: Execution Exception — Coprocessor 2 Exception.........................................................................81

4.8.18: Execution Exception — Implementation-Specific 1 Exception.......................................................81

4.8.19: Execution Exception — Integer Overflow....................................................................................... 82

4.8.20: Execution Exception — Trap.......................................................................................................... 82

4.8.21: Debug Data Break Exception.........................................................................................................82

4.8.22: Complex Break Exception..............................................................................................................83

4.9: Exception Handling and Servicing Flowcharts ..........................................................................................83

Chapter 5: CP0 Registers of the M14K™ Core ..................................................................................88

5.1: CP0 Register Summary............................................................................................................................. 88

5.2: CP0 Register Descriptions ........................................................................................................................90

5.2.1: UserLocal Register (CP0 Register 4, Select 2)................................................................................90

5.2.2: HWREna Register (CP0 Register 7, Select 0)................................................................................. 91

5.2.3: BadVAddr Register (CP0 Register 8, Select 0)................................................................................ 92

5.2.4: BadInstr Register (CP0 Register 8, Select 1)................................................................................... 92

5.2.5: BadInstrP Register (CP0 Register 8, Select 2)................................................................................93

5.2.6: Count Register (CP0 Register 9, Select 0) ......................................................................................94

5.2.7: Compare Register (CP0 Register 11, Select 0)...............................................................................94

5.2.8: Status Register (CP0 Register 12, Select 0)....................................................................................95

5.2.9: IntCtl Register (CP0 Register 12, Select 1)...................................................................................... 99

5.2.10: SRSCtl Register (CP0 Register 12, Select 2)..............................................................................103

5.2.11: SRSMap Register (CP0 Register 12, Select 3)............................................................................ 106

5.2.12: View_IPL Register (CP0 Register 12, Select 4)...........................................................................107

5.2.13: SRSMap2 Register (CP0 Register 12, Select 5).......................................................................... 107

5.2.14: Cause Register (CP0 Register 13, Select 0)................................................................................ 108

5.2.15: View_RIPL Register (CP0 Register 13, Select 4)........................................................................113

5.2.16: NestedExc (CP0 Register 13, Select 5)....................................................................................... 113

5.2.17: Exception Program Counter (CP0 Register 14, Select 0)............................................................ 114

5.2.18: NestedEPC (CP0 Register 14, Select 2)...................................................................................... 115

5.2.19: Processor Identification (CP0 Register 15, Select 0)................................................................... 116

5.2.20: EBase Register (CP0 Register 15, Select 1) ...............................................................................117

5.2.21: CDMMBase Register (CP0 Register 15, Select 2)....................................................................... 118

5.2.22: Config Register (CP0 Register 16, Select 0)................................................................................ 119

5.2.23: Config1 Register (CP0 Register 16, Select 1).............................................................................. 121

5.2.24: Config2 Register (CP0 Register 16, Select 2).............................................................................. 122

5.2.25: Config3 Register (CP0 Register 16, Select 3).............................................................................. 123

5.2.26: Config4 Register (CP0 Register 16, Select 4).............................................................................. 126

5.2.27: Config5 Register (CP0 Register 16, Select 5).............................................................................. 126

5.2.28: Config7 Register (CP0 Register 16, Select 7).............................................................................. 127

5.2.29: Debug Register (CP0 Register 23, Select 0) ...............................................................................127

5.2.30: Trace Control Register (CP0 Register 23, Select 1)....................................................................132

5.2.31: Trace Control2 Register (CP0 Register 23, Select 2)..................................................................134

5.2.32: User Trace Data1 Register (CP0 Register 23, Select 3)/User Trace Data2 Register (CP0 Register

24, Select 3).............................................................................................................................................135

5.2.33: TraceBPC Register (CP0 Register 23, Select 4) .........................................................................136

5.2.34: Debug2 Register (CP0 Register 23, Select 6) .............................................................................137

5.2.35: Debug Exception Program Counter Register (CP0 Register 24, Select 0).................................. 138

5.2.36: Performance Counter Register (CP0 Register 25, select 0-3)..................................................... 139

5.2.37: ErrCtl Register (CP0 Register 26, Select 0).................................................................................144

5.2.38: CacheErr Register (CP0 Register 27, Select 0)...........................................................................144

4 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04

5.2.39: ErrorEPC (CP0 Register 30, Select 0)......................................................................................... 145

5.2.40: DeSave Register (CP0 Register 31, Select 0).............................................................................146

5.2.41: KScratchn Registers (CP0 Register 31, Selects 2 to 3)...............................................................146

Chapter 6: Hardware and Software Initialization of the M14K™ Core...........................................149

6.1: Hardware-Initialized Processor State......................................................................................................149

6.1.1: Coprocessor 0 State ......................................................................................................................149

6.1.2: Bus State Machines.......................................................................................................................150

6.1.3: Static Configuration Inputs.............................................................................................................150

6.1.4: Fetch Address................................................................................................................................150

6.2: Software Initialized Processor State........................................................................................................ 150

6.2.1: Register File...................................................................................................................................150

6.2.2: Coprocessor 0 State ......................................................................................................................150

Chapter 7: Power Management of the M14K™ Core.......................................................................153

7.1: Register-Controlled Power Management ................................................................................................153

7.2: Instruction-Controlled Power Management.............................................................................................154

Chapter 8: EJTAG Debug Support in the M14K™ Core..................................................................155

8.1: Debug Control Register...........................................................................................................................155

8.2: Hardware Breakpoints.............................................................................................................................160

8.2.1: Data Breakpoints............................................................................................................................161

8.2.2: Complex Breakpoints.....................................................................................................................161

8.2.3: Conditions for Matching Breakpoints .............................................................................................161

8.2.3.1: Conditions for Matching Instruction Breakpoints .................................................................. 161

8.2.3.2: Conditions for Matching Data Breakpoints ........................................................................... 163

8.2.4: Debug Exceptions from Breakpoints..............................................................................................165

8.2.4.1: Debug Exception by Instruction Breakpoint.......................................................................... 165

8.2.4.2: Debug Exception by Data Breakpoint................................................................................... 165

8.2.5: Breakpoint Used as Triggerpoint.................................................................................................... 166

8.2.6: Instruction Breakpoint Registers....................................................................................................166

8.2.6.1: Instruction Breakpoint Status (IBS) Register (0x1000).........................................................167

8.2.6.2: Instruction Breakpoint Address n (IBAn) Register (0x1100 + n * 0x100)..............................167

8.2.6.3: Instruction Breakpoint Address Mask n (IBMn) Register (0x1108 + n*0x100) ..................... 168

8.2.6.4: Instruction Breakpoint ASID n (IBASIDn) Register (0x1110 + n*0x100) .............................. 168

8.2.6.5: Instruction Breakpoint Control n (IBCn) Register (0x1118 + n*0x100).................................168

8.2.6.6: Instruction Breakpoint Complex Control n (IBCCn) Register (0x1120 + n*0x100)............... 170

8.2.6.7: Instruction Breakpoint Pass Counter n (IBPCn) Register (0x1128 + n*0x100) .................... 170

8.2.7: Data Breakpoint Registers.............................................................................................................171

8.2.7.1: Data Breakpoint Status (DBS) Register (0x2000) ................................................................ 172

8.2.7.2: Data Breakpoint Address n (DBAn) Register (0x2100 + 0x100 * n).....................................172

8.2.7.3: Data Breakpoint Address Mask n (DBMn) Register (0x2108 + 0x100 * n)........................... 173

8.2.7.4: Data Breakpoint ASID n (DBASIDn) Register (0x2110 + 0x100 * n).................................... 173

8.2.7.5: Data Breakpoint Control n (DBCn) Register (0x2118 + 0x100 * n) ...................................... 173

8.2.7.6: Data Breakpoint Value n (DBVn) Register (0x2120 + 0x100 * n)......................................... 175

8.2.7.7: Data Breakpoint Complex Control n (DBCCn) Register (0x2128 + n*0x100).......................176

8.2.7.8: Data Breakpoint Pass Counter n (DBPCn) Register (0x2130 + n*0x100)............................ 177

8.2.7.9: Data Value Match (DVM) Register (0x2ffo).......................................................................... 177

8.2.8: Complex Breakpoint Registers....................................................................................................... 178

8.2.8.1: Complex Break and Trigger Control (CBTC) Register (0x8000) .......................................... 178

8.2.8.2: Priming Condition A (PrCndAI/Dn) Registers....................................................................... 179

8.2.8.3: Stopwatch Timer Control (STCtl) Register (0x8900)............................................................ 181

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 5

8.2.8.4: Stopwatch Timer Count (STCnt) Register (0x8908).............................................................182

8.3: Complex Breakpoint Usage..................................................................................................................... 182

8.3.1: Checking for Presence of Complex Break Support........................................................................ 182

8.3.2: General Complex Break Behavior.................................................................................................. 183

8.3.3: Usage of Pass Counters................................................................................................................183

8.3.4: Usage of Tuple Breakpoints...........................................................................................................184

8.3.5: Usage of Priming Conditions.......................................................................................................... 184

8.3.6: Usage of Data Qualified Breakpoints.............................................................................................185

8.3.7: Usage of Stopwatch Timers...........................................................................................................185

8.4: Test Access Port (TAP)...........................................................................................................................186

8.4.1: EJTAG Internal and External Interfaces......................................................................................... 186

8.4.2: Test Access Port Operation...........................................................................................................187

8.4.2.1: Test-Logic-Reset State.........................................................................................................188

8.4.2.2: Run-Test/Idle State............................................................................................................... 188

8.4.2.3: Select_DR_Scan State.........................................................................................................188

8.4.2.4: Select_IR_Scan State ..........................................................................................................188

8.4.2.5: Capture_DR State ................................................................................................................189

8.4.2.6: Shift_DR State......................................................................................................................189

8.4.2.7: Exit1_DR State.....................................................................................................................189

8.4.2.8: Pause_DR State...................................................................................................................189

8.4.2.9: Exit2_DR State.....................................................................................................................189

8.4.2.10: Update_DR State ...............................................................................................................189

8.4.2.11: Capture_IR State................................................................................................................190

8.4.2.12: Shift_IR State .....................................................................................................................190

8.4.2.13: Exit1_IR State..................................................................................................................... 190

8.4.2.14: Pause_IR State ..................................................................................................................190

8.4.2.15: Exit2_IR State..................................................................................................................... 190

8.4.2.16: Update_IR State.................................................................................................................190

8.4.3: Test Access Port (TAP) Instructions..............................................................................................190

8.4.3.1: BYPASS Instruction.............................................................................................................. 191

8.4.3.2: IDCODE Instruction.............................................................................................................. 191

8.4.3.3: IMPCODE Instruction ...........................................................................................................191

8.4.3.4: ADDRESS Instruction........................................................................................................... 191

8.4.3.5: DATA Instruction ..................................................................................................................192

8.4.3.6: CONTROL Instruction ..........................................................................................................192

8.4.3.7: ALL Instruction...................................................................................................................... 192

8.4.3.8: EJTAGBOOT Instruction ......................................................................................................192

8.4.3.9: NORMALBOOT Instruction ..................................................................................................192

8.4.3.10: FASTDATA Instruction .......................................................................................................193

8.4.3.11: PCsample Register (PCSAMPLE Instruction).................................................................... 193

8.4.3.12: FDC Instruction................................................................................................................... 193

8.4.3.13: TCBCONTROLA Instruction...............................................................................................193

8.4.3.14: TCBCONTROLB Instruction...............................................................................................193

8.4.3.15: TCBDATA Instruction .........................................................................................................193

8.5: EJTAG TAP Registers............................................................................................................................. 193

8.5.1: Instruction Register........................................................................................................................193

8.5.2: Data Registers Overview ...............................................................................................................194

8.5.2.1: Bypass Register ...................................................................................................................194

8.5.2.2: Device Identification (ID) Register........................................................................................ 194

8.5.2.3: Implementation Register....................................................................................................... 195

8.5.2.4: EJTAG Control Register....................................................................................................... 196

8.5.3: Processor Access Address Register..............................................................................................202

8.5.3.1: Processor Access Data Register..........................................................................................202

6 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04

8.5.4: Fastdata Register (TAP Instruction FASTDATA)........................................................................... 203

8.6: TAP Processor Accesses........................................................................................................................204

8.6.1: Fetch/Load and Store from/to EJTAG Probe Through dmseg....................................................... 205

8.7: SecureDebug...........................................................................................................................................206

8.7.1: Disabling EJTAG Debugging .........................................................................................................206

8.7.1.1: EJ_DisableProbeDebug Signal ............................................................................................206

8.7.1.2: Override for EjtagBrk and DINT Disable............................................................................... 207

8.7.2: EJTAG Features Unmodified by SecureDebug .............................................................................207

8.8: iFlowtrace™ Mechanism.........................................................................................................................207

8.8.1: A Simple Instruction-Only Tracing Scheme ...................................................................................208

8.8.1.1: Trace Inputs.......................................................................................................................... 208

8.8.1.2: Normal Trace Mode Outputs ................................................................................................208

8.8.2: Special Trace Modes .....................................................................................................................209

8.8.2.1: Mode Descriptions................................................................................................................209

8.8.2.2: Special Trace Mode Outputs................................................................................................ 211

8.8.3: ITCB Overview...............................................................................................................................212

8.8.4: ITCB iFlowtrace Interface............................................................................................................... 212

8.8.5: TCB Storage Representation.........................................................................................................213

8.8.6: ITCB Register Interface for Software Configurability .....................................................................214

8.8.6.1: iFlowtrace Control/Status (IFCTL) Register (offset 0x3fc0)..................................................214

8.8.6.2: ITCBTW Register (offset 0x3F80) ........................................................................................ 216

8.8.6.3: ITCBRDP Register (Offset 0x3f88)....................................................................................... 217

8.8.6.4: ITCBWRP Register (Offset 0x3f90)......................................................................................217

8.8.7: ITCB iFlowtrace Off-Chip Interface................................................................................................218

8.8.8: Breakpoint-Based Enabling of Tracing........................................................................................... 218

8.9: PC/Data Address Sampling..................................................................................................................... 219

8.9.1: PC Sampling in Wait State.............................................................................................................220

8.9.2: Data Address Sampling .................................................................................................................220

8.10: Fast Debug Channel..............................................................................................................................220

8.10.1: Common Device Memory Map..................................................................................................... 221

8.10.2: Fast Debug Channel Interrupt......................................................................................................221

8.10.3: M14K™ Core FDC Buffers........................................................................................................... 221

8.10.4: Sleep mode..................................................................................................................................223

8.10.5: FDC TAP Register .......................................................................................................................223

8.10.6: Fast Debug Channel Registers....................................................................................................224

8.10.6.1: FDC Access Control and Status (FDACSR) Register (Offset 0x0).....................................224

8.10.6.2: FDC Configuration (FDCFG) Register (Offset 0x8)............................................................225

8.10.6.3: FDC Status (FDSTAT) Register (Offset 0x10) ...................................................................226

8.10.6.4: FDC Receive (FDRX) Register (Offset 0x18).....................................................................227

8.10.6.5: FDC Transmit n (FDTXn) Registers (Offset 0x20 + 0x8*n)................................................ 227

8.11: cJTAG Interface.....................................................................................................................................228

Chapter 9: Instruction Set Overview.................................................................................................230

9.1: CPU Instruction Formats......................................................................................................................... 230

9.2: Load and Store Instructions.....................................................................................................................231

9.2.1: Scheduling a Load Delay Slot........................................................................................................231

9.2.2: Defining Access Types................................................................................................................... 231

9.3: Computational Instructions......................................................................................................................232

9.3.1: Cycle Timing for Multiply and Divide Instructions........................................................................... 233

9.4: Jump and Branch Instructions.................................................................................................................233

9.4.1: Overview of Jump Instructions....................................................................................................... 233

9.4.2: Overview of Branch Instructions ....................................................................................................233

9.5: Control Instructions..................................................................................................................................233