Mostek RAM-80BE Manuale utente
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Z8O IVI I CROCO MI PUTER SYSTE lVI S
Operations Manual
5
EXP\NSION
L
b
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MEMORY EXPANST0N B0ARD (RAM-808E)
(I,iKiB110)
OPERATIONS IVIANUAL
t,
l',rK7B55c
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L
SECTI ON
NUMBER
PARAGRAPH
NUMBER
t-t
t-3
t-4
t-5
l-6
2-1
2-3
2-5
2-6
2-7
2-8
2-9
2-11
2-12
2-13
2-14
?-15
3-l
3-3
?-E
3-6
3-7
10
J-O
3-9
3-t0
I
TABLE OF CONTENTS
TI TLE
GENERAL INFORMATION
I NTRODUCTI ON
GENERAL DESCRIPTION
FUNCT I ONAL
PHYSICAL
SPECIFICATIONS
FUNCTIONAL DESCRIPTION
I NTRODUCTI ON
MEMORY INTERFACE
MEIVIORY ARRAY
IVIEMORY DECODE AND CONTROL
ADDRESS MULTIPLEXER (MUX)
DATA BUFFER
PARALLEL I/O INTERFACE
plK3SUl P I0', s
PORT SELECT
BIDIRECTIONAL BUFFERS
STRAPP ED BUF FEP.S
DATA AND CONTROL BUFFERS
UTI LIZATION
INTRODUCTION
PARALLEL INTERFACE
CONNECTORS
RESISTOR TERMINATIONS
HANDSHAKE LINE BUFFERS (STB, RDY)
PORT A DATA BUFFER
PORT B DATA BUFFER
HEADER AND JUMPER INFORMATION
PAGE
NUMBER
1-1
1-1
I -t
I -t
1-1
2-1
2-1
2-1
z-1
2-1
2-1
2-3
o')
2-3
t-3
2-3
z-3
3-t
3-t
3-t
3-t
3-t
3-3
3-3
3-4
2
!
1t
SECTION
NUMBER
3 CONT'tl
APPENDIX A
APPENiJIX B
APPEI'iDIX C
PARAGRAPH
NUMBER
3-t I
3-12
3-t3
3-t5
3-t 6
3-17
a 1()
J-lo
3-t9
TABLE 0F C0NTENTS (C0NTD)
TITLE
PORT ADDRESSES
HEADER ANI] JUMPER iNFORMATI(-)N
MEMORY INTERFACE
MEMORY iJECijDING JUiviPERS
PAGE MODE
HTADER ANI] JUMPER INFORMATI(]N
MEIVIORY DISABLE iNPUTS
ADDIIIG MEiVlOiiY T() THI RAIVi-IJ(]B USING
THE XRAM-I]OB ADD ON P]EI,IORY PACKAGE
FACTORY NOTICES
SCHEMATIC DIAGRAMS
ASSEMBLY
\,
PAGE
NUMBER
2(r
J-U
3-13
3-13
3- 13
3-17
3-17
3-17
3-22
A-1
B-1
c-1
v
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jjj
5LIST OF FIGURES
TITLE
RAM.SOBE CIRCUIT BOARD
RAM-8OBE FUNCTIONAL BLOCK DIAGRAM
GENERALIZED PARALLEL I/O INTERFACE
STRAPS TO CONTROL PARALLEL PORTS
PARALLEL I/O INTERFACE #I AS SHIPPED FROM THE FACTORY
PARALLEL I/O INTERFACE #2 AS SHIPPED FROM THE FACTORY
PARALLEL I/O INTERFACE
PARALLEL I/O INTERFACE
DECODED PORTS AVAILABLE FOR PIO #I, PIO #2, AND PAGE MODE
HEADER STRAPPING OPTIONS FOR PIO #I, PIO #2, AND PAGE MODE
PORT SELECT
HEADER STRAPPING OPTIONS FOR POSITIONING RAM-8OBE MEMORY
SDB-80E SYSTEM USING F0UR RAM-808E's IN PAGE M0DE
STRAPPING FOR ENABLING AND DISABLING PAGE MODE
HEADER STRAPPING OPTIONS FOR PAGE SELECT O-7
HEADER STRAPPING OPTIONS FOR PAGE SELECT 8.F
SDB-8OE CONFIGURED TO DISABLE OVERLAPPING RAM.SOBE MEMORY
F I GURE
NUMBER
I -l
2-1
3-t
,) ,)
J-J
3-4
5-O
3-7
3-8
3-9
3-t0
3-t I
3-12
3- 13
3 -14
PAGE
NUMBER
1-2
?-2
3-2
3-6
3-9
3-l 0
3-t I
3-12
3- 14
3- 15
L3-16
3-t8
3-t9
3-?O
3-21
3-?3
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iv
TABLE
NUMBER
t-t
1-2
l-3
3-t
.) ,)
J-L
3-3
3-4
2r:
3-6
3-7
LIST OF TABLES
TITLE
AVAILABLE ITEMS
SPECIFICATIONS
CONNECTOR SKl & SKz PIN OUT
STRAPPING OF HANDSHAKE BUFFERS AS SHIPPED FROM FACTORY
DEVICE OPTIONS FOR PORT B
JUMPER OPTIONS FOR HANDSHAKE BUFFERS
JUMPER OPTIONS FOR PORT B CONTROL LINES
JUMPER OPTIONS F()R PORT A CONTROL LINES
DECODED PORTS AVAILABLE FOR PIO #I, PIO #2, AND PAGE MODE
EXPANDING RAIVI-8OBE MEMORY
\,
PAGE
NUMBER
t-3
t-3
l-4
3-3
3-4
3-5
3-7
1o
3- 13
3-24
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SECTION 1
GENERAL INFORMATION
I.I . INTRODUCTiON.
1-2. The RAN'I-BCBE shown in Figure l-l provides a low cost nreans of expanding RAl4
and para11e1 I/0 for a ZB0 microcomputer systenr. The RAPl-80tsE is a peripheral
board wh'i ch can be d i rect'ly 'i nte rf aced to t he M0STEK ZB0 Sof tware Devel opme nt
Board (SDB-B0E) or any ZB0 Microprocessor based system.
I-3. GENERAL DESCRIPTION.
l-4. FUNCTI0i'lAL. The RAl,i-B0BE is a cornbj nat jon n:emory and I/0 expansion board.
The mernory niay be configured to have a rilemory capacity of l6K, 32K,48K, or 65K
bytes of RAivi. This on-board memory expandabil ity is rnade possible by population
options of ejther eight, sixteen, twenty-four or thirty-two i,lK4l l6-4 (16,384x1 i\10S
dynarnic RAI"I) menrories. The RAM-B0BE provides strapping options for positioning
the decoded memory space to start on any l6K address boundary. In addjtion to the
add-on memory, the RAM-B0BE provides four B-bit I/0 ports from the two on-board
l,iK3BBl ZB0 PI0 circuits. Each I/0 port 'is fu11y TTL buf fered and has two
handshake ljnes per I/0 port. The RAM-B0BE also includes logic for a "Page Mode
0peration" which permits up to l rnega-byte (sixteen 65KxB RAltl-B0B[s) to be used'in
a singie SDB-B0E system.
l-5. PHYSICAL. The RAM-B0BE is implenrented on a double Eurocard pri nted ci rcur't
board. The board requires three DC voltages at levels of +5, +12, and -12 VDC.
The RAIvI-B0BE'is interfaced to a system by connectors SKl and SK2.
I.6. SPECIFICATIONS.
1-7. Table l-l I ists nornenclature and part numbers for tlre RAM-B0BE and 'its
accessorjes. Table l-2 lists the overal 1 specif jcations for the RAivl-B0BE. Table
l-3 lists the pin usage of connectors SKl and SK2.
tt
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t-2
Figure 1-1. RAM-B0BE Board. \r
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I
t-3
\, Table 1-1. Available Items
Table 1-2. Specifications.
L
b
NAME
RAM.BOBE
**
DESCRIPTI ON
Expandable .l6,384 byte RAM board with 8-MK4116s,
sockets for 24 addjtional MK4ll6s, 2-MK38B1 ZB0
PI0s, p1 us page mode capabi 1 i ty.
PART NO
MK7B1 10
XRAM-BOB** RAM-B0Bt Expans ion Package, i ncl udes B-MK4l l6 RAMs MKTBI 26
for j nsert1on 'in the RAM-B0BE board pl us a blank
strappi ng header and document at'ion.
The XRAM-BOB package is available to RAM-B0BE customers only. It is therefore
required that each order for an XRAM-B0B be accornpanied by an /\uthorization
Cert'ifjcate from the RAM-B0BE package. (Each RAM-B0BE package is shipped with
three of these non-transferable, non-replaceable certificates. )
Mernory Capaci ty
I'lemory Acces s
Mernory Cyc 1e
Paral lel I/O
Interface levels
Physical Djrrensions
0perat i ng Ternperature
Up to 65,536 bytes
345 ns max.
450 ns min.
Four 8-bjt ports w/handshake lines
TTL compatible
+12 VDC +_5%,200 rnA (typ); 575 mA (max)
-12 VDC +_ 57,, 25 mA (typ); 30 mA (rnax)
+5 VDC +_5%, l.lA (typ);.|.5 A (max)
250 mnr x 233.4 rnr x 18 mm
0Cto50C
t-4
GND
GNt)
-t2Y
+5V
+5V
+t2v
I EOB
RESETI]
iVlR EQB
I I\TB
DB
I ORQB
WRB
R FSHB
DINB
Table 1-3. Connector SK1 and SK2 Pin Out. \
c
a
C
a
SK1
10
11
T2
13
74
1(
16
t7
1()
IU
19
20
2l
LL
)').
,) /t
L+
25
sK2
11
t2
13
t4
15
16
l1
1B
19
20
Z1
22
c')
LJ
24
25
1
2
a
J
1
2
a
J
4
5
4
5
6
7
B
GND
GND
-l2u
+5V
+5V
+l2Y
IEIB
MEIviD I 52
IliEMD I SB
t41B
RDB
AOB
AiB
A2B
A3B
A4B
A5B
A6B
ATrl
A8B
GND
GND
RD Y2B
P (D6 )4
P(D6)5
P (D6 )6
P(D6)7
RDY2A
P (D4 )4
GND
GND
\
BAI9
BAO
PD4) 5
D4 )6
D4)7
STB28
P (D6 )3
P (D6 )2
P(D6)1
P (D6 )o
STB2A
P (D2 3
P(D4)3
P(D4)2
P(D4)o
\
STBlB
PP(D4)1
P
RDYlB
P (D2 )4
P (D2 )5
D()B P (D?)2
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