National Instruments 5762R Manuale utente

NI 5762R User Guide and Specifications

The NI 5762 is a two-channel, 250 MS/s, 16-bit high-speed digitizer adapter module designed to work

in conjunction with your NI FlexRIO™FPGA module. The NI 5762 is available in these two versions:

• NI 5762 (-01): Single-ended, AC-coupled with a 100 MHz elliptic filter

• NI 5762 (-02): Single-ended, AC-coupled, ideal for undersampling applications

Read the white labels on the side of your device to determine which version of the NI 5762 you are

using. This document contains signal information and specifications for the NI 5762R, which is

composed of an NI FlexRIO FPGA module and the NI 5762. This document also contains tutorial

sections that demonstrate how to acquire data using a LabVIEW FPGA example VI and how to create

and run your own LabVIEW project with the NI 5762R.

Contents

Electromagnetic Compatibility Guidelines.......................................................................................... 2

How to Use Your NI FlexRIO Documentation Set ............................................................................. 3

Front Panel and Connector Pinouts ..................................................................................................... 4

Block Diagram ..................................................................................................................................... 6

NI 5762 Component-Level Intellectual Property (CLIP) .................................................................... 7

Cables................................................................................................................................................... 9

Clocking............................................................................................................................................... 9

Using Your NI 5762R with a LabVIEW FPGA Example VI.............................................................. 9

Creating a LabVIEW Project and Running a VI on an FPGA Target ................................................. 11

Specifications....................................................................................................................................... 15

Where to Go for Support ..................................................................................................................... 24

Appendix: Installing EMI Controls ..................................................................................................... 25

Note Before configuring your NI 5762R, you must install the appropriate software and hardware.

Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for installation

instructions. Figure 1 shows an example of a properly connected NI FlexRIO device.

Figure 1. NI FlexRIO Device

Note NI 5762R refers to the combination of your NI 5762 adapter module and your NI FlexRIO

FPGA module. NI 5762 refers to your NI 5762 adapter module only.

NI FlexRIO

Adapter Module + = NI FlexRIO Device

NI FlexRIO

FPGA Module

NI 5762R User Guide and Specifications 2 ni.com

Electromagnetic Compatibility Guidelines

This product was tested and complies with the regulatory requirements and limits for electromagnetic

compatibility (EMC) as stated in the product specifications. These requirements and limits are designed

to provide reasonable protection against harmful interference when the product is operated in its

intended operational electromagnetic environment.

This product is intended for use in industrial locations. There is no guarantee that harmful interference

will not occur in a particular installation, when the product is connected to a test object, or if the product

is used in residential areas. To minimize the potential for the product to cause interference to radio and

television reception or to experience unacceptable performance degradation, install and use this product

in strict accordance with instructions in the product documentation.

Furthermore, any changes or modifications to the product not expressly approved by National

Instruments could void your authority to operate it under your local regulatory rules.

Caution To ensure the specified EMC performance, you must install PXI EMC Filler Panels

(National Instruments part number 778700-01) in adjacent chassis slots. For more information about

installing PXI EMC filler panels on your NI 5762R, refer to the Appendix: Installing EMI Controls

section of this document.

Caution To ensure the specified EMC performance, operate this product only with shielded cables

and accessories.

Caution To ensure the specified EMC performance, install the included snap-on ferrites (National

Instruments part number 711856-01) on any cable attached to the AUX I/O connector in accordance

with the instructions listed in the Appendix: Installing EMI Controls section.

Caution This product is sensitive to electrostatic discharge (ESD). To ensure the specified EMC

performance, follow the programming instructions listed at the end of the Using Your NI 5762R with

a LabVIEW FPGA Example VI and Creating a LabVIEW Project and Running a VI on an FPGA

Target sections of this document.

©National Instruments Corporation 3 NI 5762R User Guide and Specifications

How to Use Your NI FlexRIO Documentation Set

Refer to Figure 2 and Table 1 for information about how to use your NI FlexRIO documentation set.

Figure 2. How to Use Your NI FlexRIO Documentation Set

Table 1. NI FlexRIO Documentation Locations and Descriptions

Document Location Description

NI FlexRIO FPGA

Module Installation

Guide and Specifications*

Available in your FPGA module

hardware kit and from the Start Menu.

Contains installation instructions for your

NI FlexRIO system and specifications for your

FPGA module.

NI Adapter Module User

Guide and Specifications*

Available in your adapter module

hardware kit and from the Start Menu.

Contains signal information, examples, and

specifications for your adapter module.

LabVIEW FPGA Module

Help*

Embedded in LabVIEW Help.Contains information about the basic functionality of

LabVIEW FPGA Module.

NI FlexRIO Help*Embedded in LabVIEW FPGA

Module Help.

Contains FPGA module, adapter module, and CLIP

configuration information.

LabVIEW Examples Available in NI Example Finder. Contains examples of how to run FPGA VIs and

Host VIs on your device.

Other Useful Information on ni.com

ni.com/ipnet Contains LabVIEW FPGA functions and intellectual property to share.

ni.com/flexrio Contains product information and data sheets for NI FlexRIO devices.

* These documents are also available at ni.com/manuals.

LabVIEW FPGA

Module Help

NI FlexRIO

Help

LabVIEW

Examples

INSTALL Hardware

and Software

CONNECT Signals

and Learn About

Your Adapter

Module

LEARN About

LabVIEW FPGA

Module

PROGRAM Your

NI FlexRIO System

in LabVIEW FPGA

Module

NI FlexRIO FPGA Module

Installation Guide and Specifications

NI xxxxR User Guide

and Specifications

Are

You New to

LabVIEW FPGA

Module?

Yes No

NI 5762R User Guide and Specifications 4 ni.com

Front Panel and Connector Pinouts

Table 2 shows the front panel connectors and signal descriptions for both versions of the NI 5762. Refer

to the Specifications section of this document for additional signal information.

Caution To avoid permanent damage to the NI 5762, disconnect all signals connected to the NI 5762

before powering down the module, and connect signals only after the adapter module has been

powered on by the NI FlexRIO FPGA module.

Caution Connections that exceed any of the maximum ratings of any connector on the NI 5762R

can damage the device and the chassis. NI is not liable for any damage resulting from such signal

connections. For the maximum input and output ratings for each signal, refer to the Specifications

section of this document.

Table 2. NI 5762 Front Panel Connectors

Device Front Panel Connector Signal Description

AI 0 Single-ended analog input channel 0.

TRIG External trigger input.

CLK IN*Reference or external clock input.

AI 1 Single-ended analog input channel 1.

AUX I/O Refer to Table 3 for the signal list and descriptions.

* When not using an external Sample clock or the Reference clock, terminate the CLK IN input connector with a 50 Ω

terminator. Failing to terminate the CLK IN connector may negatively impact the jitter performance of the NI 5762.

TRIG

CLK IN

AUX

I/O

NI 5762

INSTRUMENTS

NATIONAL

250 MS/s

Digitizer

©National Instruments Corporation 5 NI 5762R User Guide and Specifications

AUX I/O Connector

Table 3 shows the pin assignments for the AUX I/O connector on the NI 5762.

Caution The AUX I/O connector accepts a standard, third-party HDMI cable, but the AUX I/O port

is not an HDMI interface. Do not connect the AUX I/O port on the NI 5762 into the HDMI port of

another device. NI is not liable for any damage resulting from such signal connections.

Table 3. NI 5762 AUX I/O Connector Pin Assignments

AUX I/O Connector Pin Signal Signal Description

1 DIO Port 0 (0) Bidirectional single-ended digital I/O data channel.

2 GND Ground reference for signals.

3 DIO Port 0 (1) Bidirectional single-ended digital I/O data channel.

4 DIO Port 0 (2) Bidirectional single-ended digital I/O data channel.

5 GND Ground reference for signals.

6 DIO Port 0 (3) Bidirectional single-ended digital I/O data channel.

7 DIO Port 1 (0) Bidirectional single-ended digital I/O data channel.

8 GND Ground reference for signals.

9 DIO Port 1 (1) Bidirectional single-ended digital I/O data channel.

10 DIO Port 1 (2) Bidirectional single-ended digital I/O data channel.

11 GND Ground reference for signals.

12 DIO Port 1 (3) Bidirectional single-ended digital I/O data channel.

13 PFI 0 Bidirectional single-ended digital I/O data channel.

14 NC No connect.

15 PFI 1 Bidirectional single-ended digital I/O data channel.

16 PFI 2 Bidirectional single-ended digital I/O data channel.

17 GND Ground reference for signals.

18 +5V +5 V power (10 mA, maximum).

19 PFI 3 Bidirectional single-ended digital I/O data channel.

NI 5762R User Guide and Specifications 6 ni.com

Block Diagram

Figure 3 shows a block diagram image of the signal flow to and from the NI 5762 adapter module and

the NI 5762 component-level intellectual property (CLIP) in LabVIEW FPGA.

Figure 3. NI 5762 Connector Signals and NI 5762 CLIP Signal Block Diagram

NI 5762 Adapter Module

AI 0

AI 1

TRIG

CLK IN

DIO Port 0 (0)

DIO Port 0 (1)

DIO Port 0 (2)

DIO Port 0 (3)

DIO Port 1 (0)

DIO Port 1 (1)

DIO Port 1 (2)

DIO Port 1 (3)

PFI 0

PFI 1

PFI 2

PFI 3

AUX I/O

AD9647

Analog

Path

ADC Clock

ADC Data

ADC Control

Clk Function

PLL Locked

Enable VCX0

SClk

I2C (Shared)

Sda

Clk Control

Sample Clock

AD9647

AD9511

LabVIEW FPGA CLIP

Analog

Path

PLL Loop

Filter

ADT7408

Temperature

Sensor

User

EEPROM

250 MHz

VCXO

Enable PLL

ADC Clock

ADC Data

ADC

Interface

ADC

Interface

AI 0 Data (N and N-1)

AI 1 Data (N and N-1)

Trigger Input

Sync Clock (IoModSyncClk)

PLL Locked

Initialization Done

Reinitialize

AI 0 Data Over Range

AI 1 Data Over Range

Configuration Error

Configuration Error Code

SPI Device Select

SPI Read

SPI Write

SPI Write Data

SPI Address

SPI Read Data

SPI Idle

SPI Engine

DIO Port 0 WE

DIO Port 0 Rd Data (0)

DIO Port 0 Wr Data (0)

DIO Port 0 Rd Data (1)

DIO Port 0 Wr Data (1)

DIO Port 0 Rd Data (2)

DIO Port 0 Wr Data (2)

DIO Port 0 Rd Data (3)

DIO Port 0 Wr Data (3)

DIO Port 1 Rd Data (0)

DIO Port 1 Wr Data (0)

DIO Port 1 Rd Data (1)

DIO Port 1 Wr Data (1)

DIO Port 1 Rd Data (2)

DIO Port 1 Wr Data (2)

DIO Port 1 Rd Data (3)

DIO Port 1 Wr Data (3)

DIO Port 1 WE

PFI 3 Wr Data

PFI <0..3> WE

PFI 3 Rd Data

PFI 1 Rd Data

PFI 1 Wr Data

PFI 2 Rd Data

PFI 2 Wr Data

PFI 0 Rd Data

PFI 0 Wr Data

Sample Clock Select

Sample Clock Commit

User EEPROM Write Data Successful

User EEPROM Address

User EEPROM Read

User EEPROM Write

User EEPROM Read Data

Measure Temperature

I2C Timeout

Temperature

Temperature Valid

User EEPROM Read Data Valid

User EEPROM Write Data

©National Instruments Corporation 7 NI 5762R User Guide and Specifications

NI 5762 Component-Level Intellectual Property (CLIP)

The LabVIEW FPGA Module includes a feature for HDL IP integration called CLIP. NI FlexRIO

devices support two types of CLIP: user-defined and socketed.

•User-defined CLIP allows users to insert HDL IP into an FPGA target, enabling VHDL code to

communicate directly with an FPGA VI.

•Socketed CLIP provides the same IP integration functionality of the user-defined CLIP, but it also

allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter module

socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external

adapter module connector interface.

Figure 4 shows the relationship between an FPGA VI and CLIP.

Figure 4. CLIP Relationship

Adapter Module

CLIP Socket

LabVIEW

FPGA VI

User-Defined

CLIP

NI FlexRIO FPGA Module

FPGA

External

I/O Connector

Adapter

Module

Socketed

CLIP

User-Defined

CLIP Fixed I/O

DRAM 0

CLIP Socket

Socketed

CLIP

DRAM 1

CLIP Socket

Socketed

CLIP

Fixed I/O

DRAM0 DRAM1

NI 5762R User Guide and Specifications 8 ni.com

The NI 5762 ships with socketed CLIP items that are used to add module I/O to the LabVIEW project.

The NI 5762 ships with the following CLIP items:

•NI 5762 Multiple Sample CLIP—This CLIP generates two samples per clock cycle at a clock rate

that is half the sample rate. The default sample rate is 250 MHz, which sets the default clock rate

for this CLIP at 125 MHz. You can set a lower sample rate by using an external Sample clock. This

CLIP provides access to two analog input channels, eight DIO lines, four PFI lines, and an input

clock selector that can be configured to use one of the following settings:

– Internal Sample clock

– Internal Sample clock locked to an external Reference clock through Sync Clock

(IoModSyncClk)

– Internal Sample clock locked to an external Reference clock through the CLK IN connector

– External Sample clock through the CLK IN connector

This CLIP also contains an engine to program the clock chip and ADCs, either through predetermined

settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced

setup. Additionally, this CLIP provides an I2C interface to access a user EEPROM and a temperature

sensor. In the LabVIEW FPGA Module, each analog signal uses a signed I16 data type. The DIO signals

are grouped into two ports of four signals each and are accessed using a U8 data type and Boolean write

enable signal. The four PFI signals are accessed individually using Boolean controls.

The NI 5762 Multiple Sample CLIP is the default CLIP.

•NI 5762 Single Sample CLIP—This CLIP generates one sample per clock cycle at a default

sample rate of 250 MHz. You can set a lower sample rate by using an external Sample clock. This

CLIP provides access to two analog input channels, eight digital input/output lines, four PFI lines,

and an input clock selector that can be configured to use one of the following settings:

– Internal Sample clock

– Internal Sample clock locked to an external Reference clock through Sync Clock

(IoModSyncClk)

– Internal Sample clock locked to an external Reference clock through the CLK IN connector

– External Sample clock through the CLK IN connector

This CLIP also contains an engine to program the clock chip and ADCs, either through predetermined

settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced

setup. Additionally, this CLIP provides an I2C interface to access a user EEPROM and a temperature

sensor. The DIO signals are grouped into two ports of four signals each and are accessed using a U8 data

type and Boolean write enable signal. The four PFI signals are accessed individually using Boolean

controls.

Refer to the NI FlexRIO Help for more information about NI FlexRIO CLIP items, configuring the

NI 5762 with a socketed CLIP, and a list of available socketed CLIP signals.

©National Instruments Corporation 9 NI 5762R User Guide and Specifications

Cables

Use any shielded 50 Ω coaxial cable with an SMA plug end to connect to the AI 0, AI 1, EXT TRIG,

and CLK IN connectors on the NI 5762 front panel.

Use any HDMI cable with the two provided cable ferrites to connect to the digital I/O and PFI signals

on the AUX I/O connector. Refer to the Appendix: Installing EMI Controls section for more information

about attaching cable ferrites.

For more information about connecting I/O signals on your device, refer to the Specifications section of

this document.

Clocking

The NI 5762 clocks control the sample rate and other timing functions on the device. Table 4 contains

information about the possible NI 5762 clock resources. For more clocking information, refer to the

CLK IN section of the specifications.

Using Your NI 5762R with a LabVIEW FPGA Example VI

Note You must install the software before running this example. Refer to the NI FlexRIO FPGA

Module Installation Guide and Specifications for more information about installing your software.

The NI FlexRIO Adapter Module Support software includes a variety of example projects to help get

you started creating your LabVIEW FPGA application. This section explains how to use an existing

LabVIEW FPGA example project to generate and acquire samples with the NI 5762R. This example

requires at least one SMA cable for connecting signals to your NI 5762R.

Note The examples available for your device are dependent on the version of the software and driver

you are using. For more information about which software versions are compatible with your device,

visit ni.com/info and enter rdsoftwareversion as the Info Code.

Each NI 5762R example project includes the following components:

• A LabVIEW FPGA VI that can be compiled and run on the FPGA embedded in the hardware. This

VI is referred to as the FPGA Target VI.

• A VI that runs on Windows that interacts with the LabVIEW FPGA VI. This VI is referred to as

the Host VI.

Table 4. NI 5762 Clock Sources

Clock Frequency Description

Internal Clock

PLL Off

250 MHz The internal VCXO acts as a free-running clock.

Internal Clock

PLL On

(IoModSyncClk)

250 MHz The internal VCXO locks to PXI_CLK10 through Sync Clock

(IoModSyncClk), which is provided only through the backplane

of NI PXIe-796xR devices.

Internal Clock

PLL On

(CLK IN)

250 MHz The internal VCXO locks to an external Reference clock

(10 MHz), which is provided through the CLK IN front panel

connector.

External Clock

(CLK IN)

150 MHz to 250 MHz An external Sample clock can be provided through the CLK IN

front panel connector.

NI 5762R User Guide and Specifications 10 ni.com

Note In the LabVIEW FPGA Module software, NI FlexRIO adapter modules are referred to as

IO Modules.

Complete the following steps to run an example that acquires a waveform on AI 0 of the NI 5762.

1. Connect one end of an SMA cable to AI 0 on the front panel of the NI 5762 and the other end of

the cable to your device under test (DUT).

2. Launch LabVIEW.

3. In the Getting Started window, click Find Examples to display the NI Example Finder.

4. In the NI Example Finder window, select Hardware Input and Output»FlexRIO»

IO Modules»NI 5762 (-0x).(Where xcorresponds with the hardware version of the NI 5762 you

are using.)

5. Select NI 5762 (-0x)- Getting Started.lvproj.

6. In the Project Explorer window, open NI 5762 - Getting Started (Host).vi under My Computer.

The host VI opens. The Open FPGA VI Reference function in this VI uses the NI 7952R as the

FPGA target by default. If you are using an NI FlexRIO FPGA module other than the NI 7952R,

complete the following steps to change to the FPGA VI to support your target.

a. Select Window»Show Block Diagram to open the VI block diagram.

b. On the block diagram, right-click the Open FPGA VI Reference (PXI-7952R) function and

select Configure Open FPGA VI Reference.

c. In the Configure Open FPGA VI Reference dialog box, click the Browse button next to the

Bitfile button.

d. In the Select Bitfile dialog box that opens, select the bitfile for your desired target. The bitfile

name is based on the adapter module, example type, and FPGA module.

e. Click the Select button.

f. Click OK in the Configure Open FPGA VI Reference dialog box.

g. Save the VI.

7. On the front panel, in the RIO Resource pull-down menu, select an NI 5762R resource that

corresponds with the target configured in step 6.

8. Select AI 0 in the AI Channel control.

9. Set the Trigger Level (V), Record Size, Sample Rate, and Range (V) controls to the desired

value.

10. In the Trigger Type control, you can select either Software Trigger or Data Edge. If you select

Software Trigger, the VI acquires data every time you click the Software Trigger button on the

front panel of the VI. If you select Data Edge, the VI acquires data every time an edge occurs.

11. Click the Run button to run the VI.

12. Click the Software Trigger button if you selected Software Trigger in the Trigger Type control.

The VI acquires data and displays the captured waveform on the Acquired Waveform graph as

shown in Figure 5.

13. Click the STOP button to stop the VI.

14. Close the VI.

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