Network DWC-HD-DMUX Manuale utente

network-electronics.com

HD-SDI to SD-SDI

Down-converter

Rev. 2

Flashlink User Manual

DWC-HD

DWC-HD Rev. 2

Network Electronics AS

Nordre Kullerød 1

P.O. Box 1020

N-3204 Sandefjord, Norway

Phone: +47 33 48 99 99

Fax: +47 33 48 99 98

Email: [email protected]

www.network-electronics.com

Support Phone: +47 90 60 99 99

Revision history

Current revision of this document is the uppermost in the table below.

Rev. Repl. Date Sign Change description

2 1 2008-07-09 NBS Added Block diagram in Chapter 1.

1 0 2008-06-18 NBS Removed monitoring versions.

0 - 2008-06-12 TB First version for public release.

network-electronics.com | 2

DWC-HD Rev. 2

Contents

.......................................................................................................... 2Revision history

..................................................................................................................... 3Contents

1.......................................................................................... 5Product overview

.......................................................................................................51.1 Product versions

2............................................................................................... 7Specifications

3................................................................................................. 10Description

................................................................................................................103.1 Data path

......................................................................................................103.1.1 Audio data path

...........................................................................103.1.2 When down-converting HD video

......................................................................103.1.3 When frame synchronizing SD video

............................................................................................113.2 Video blocks overview

............................................................................113.3 Optical/ Electrical input selection

..............................................................................................................113.4 De-glitcher

..........................................................................................................123.5 Scaling block

................................................................................................123.6 Frame synchronizer

..................................................................................................133.6.1 Frame Sync mode

..................................................................................................143.6.2 Frame delay mode

......................................................................................................143.7 Video generator

...........................................................................................153.8 Video processing block

.......................................................................................................153.8.1 Gain and offset

..........................................................................................153.8.2 Video payload legalizer

............................................................................................153.9 EDH processing block

............................................................................................153.10 Video output selection

..............................................................................................................153.11 Video DAC

.......................................................................................................173.12 Audio overview

................................................................................................173.13 Audio de-embedder

.............................................................................................................173.14 Audio delay

.........................................................................................173.15 Audio cross point matrix

.............................................................................................173.16 Audio fallback options

......................................................................................................173.17 Audio generator

...........................................................................................183.18 Audio processing block

.....................................................................................................183.19 Audio embedder

................................................................................................183.20 Analog audio output

4.............................................................................................. 19Configuration

...............................................................................................194.1 DIP switch functions

........................................................................................204.2 FACTORY reset function

..............................................................................214.2.1 Rotary switch and push buttons

.........................................................................................................214.2.2 Slide switches

...........................................................................................................214.3 GYDA mode

.....................................................................................................214.3.1 Information page

.................................................................................................224.3.2 Configuration page

5............................................................................................... 23Connections

6................................................................................................... 24Operation

.....................................................................................246.1 Front panel LED indicators

..................................................................................................246.2 RS422 commands

...................................................................................246.2.1 FLP4.0 required commands

.............................................................................................266.2.2 Normal control blocks

..........................................................316.2.3 Commands intended for debug/lab use only

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DWC-HD Rev. 2

................ 32General environmental requirements for Network Electronics equipment

...................................................................................................... 33Product Warranty ...........................34Appendix A Materials declaration and recycling information

.............................................................................34A.1 Materials declaration

............................................................................34A.2 Recycling information

................................................................................... 35EC Declaration of Conformity

network-electronics.com | 4

DWC-HD Rev. 2

1 Product overview

The Flashlink DWC-HD-DMUX converts an HD-SDI input signal to an SD-SDI output signal

with user selectable aspect ratio.

Four digital outputs and a set of configurable analog video outputs are provided, all of which

can be set to output the SD signal or the re-clocked original HD signal.

For SD input the card will act as an SD frame synchronizer with an adjustable delay relative

to the sync signal. This frame synchronizer functionality is also present when down-

converting. The card is prepared to accept black & burst or a tri-level signal from the frame.

The DWC-HD-DMUX also has a de-glitcher to give error-free synchronous switching.

The audio embedded in the HD-SDI or SD-SDI stream is de-embedded and can be delayed

relative to video. Each audio channel can be swapped in an audio matrix before they are re-

embedded in the SD-SDI data output stream. For SD-SDI inputs it is possible to turn

embedding completely off and leave the SDI stream unaltered.

A selection of user parameters of the card can be controlled by switches on the board.

Complete control of all parameters is available by use of the Flashlink RS422 Control

Protocol Version 4, which is supported by the Gyda system controller from software release

2.13.

Figure 1: DWC-HD-DMUX-R block diagram

1.1 Product versions

DWC-HD HD down-converter. With 2XSDI out, SD/HD analog out, internal

audio handling, and frame synchronizer functionality.

DWC-HD-R HD down-converter. With high sensitivity 9/125µm single mode

optical input, 2XSDI out, SD/HD analog out, internal audio handling,

and frame synchronizer functionality.

DWC-HD-DMUX HD down-converter. With 2XSDI out, SD/HD analog out, internal

audio handling, analog stereo out, AES (or RS-422 data) out, and

frame synchronizer functionality.

network-electronics.com | 5

DWC-HD Rev. 2

DWC-HD-DMUX-R HD down-converter. With high sensitivity 9/125µm single mode

optical input, 2XSDI out, SD/HD analog out, internal audio handling,

analog stereo out, AES (or RS-422 data) out, and frame

synchronizer functionality.

network-electronics.com | 6

DWC-HD Rev. 2

2 Specifications

Optical SDI input

Data rate optical: 270 – 1485 Mbps

Sensitivity

- HD-SDI (1485 Mbps): Better than -22dBm

- SD-SDI (270 Mbps): Better than -22dBm

Detector overload threshold: Min. -3dBm

Detector damage threshold: >+1dBm

Optical wavelength: 1200-1620nm

Transmission circuit fiber: 9/125um Single Mode

Connector return loss: >40dB w/ SM fiber

Connector: SC/UPC

Electrical SDI input

Connectors 75 Ohm BNC

Equalization Automatic:

->300m @270Mbps w/Belden 8281, BER < 10E-12

->100m @1485Mbps w/Belden 1694A, BER < 10E-12

Input Return loss >15dB, 5MHz -1.5GHz

-SD limit:Jitter tolerance -10Hz-1kHz: >1 UI

-10kHz – 5MHz: >0.2 UI

-HD limit:

-10Hz-100kHz: >1 UI

-100kHz–10MHz: >0.2 UI

Electrical Sync input

Connector 75 Ohm BNC

Format Black & Burst, Tri-level

Input Return loss <-35dB @ < 10MHz,

30dB @ < 30MHz

Electrical SDI outputs

Number of outputs 2

Connectors 75 Ohm BNC

Output Return loss >15dB, 5MHz -1.5GHz

Output signal level 800mV +/- 10%

-SD limit: [0.4ns – 1.5ns]; <0.5ns rise/fall var.Output signal rise / -HD limit: < 270ps, <100ps rise/fall var.fall time, 20% - 80%

Amplitude overshoot <10%

-SD: <0.2 UIOutput timing jitter -HD: <1 UI

-SD: <0.15 UIOutput alignment jitter -HD: <0.15 UI

Analog Video output, NTSC/PAL

Number of outputs 1 Component RGB/ YUV or 3 CVBS

Connector 3 x 75R BNC

DC offset < 0±15mV

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DWC-HD Rev. 2

White level, NTSC 100±1 IRE

Sync level, NTSC 40±1 IRE

Return loss > 35dB @ 10MHz, >40dB @ 5MHz

White level, PAL 100±1 IRE

Sync level, PAL 40±1 IRE

Diff gain <0.5%

Diff phase <1deg

AM noise < -60dB

PM noise < -60dB

S/N < -60dB

2T K-factor < 0.5%

(2T pulse distortion)

Luma non-linearity < 2%

Analog Video output, HD

Number of outputs 1 component RGB/ YPbPr

Connector 3 x 75R BNC

DC offset < 0±15mV

White level 100±1 IRE

Return loss > 30dB @ 30MHz

Analog Audio output

Number of outputs 1 stereo pair

Connectors 2 x WECO audio connectors

Impedance < 66R

Dynamic range >100dB(A)

Crosstalk < -60dB 20Hz-20kHz

THD+N -70dB

Frequency response 20Hz-20kHz +/- 0.5dB

Output level 24dBu +/- 1dB

Common mode DC 0 – 48V

immunity

Level adjustment range 0 – 24dBu with 1db step

Two tone intermodulation < -80dB

AES output

Number of outputs 1

Connectors WECO audio connector

Return loss 110R +/-20% 0.1MHz – 6.144MHz

Output jitter <0.0025UI peak

Supported standards

SD, 270 Mbps SMPTE 259M, SMPTE 272M-AC

HD, 1485 Mbps SMPTE 292M, SMPTE 274M, SMPTE 291M, SMPTE 296M,

SMPTE 299M

Analog video SMPTE 170M, SMPTE 274M, ITU-R. BT.470,

ITU-R. BT.709 Part 2

Centre of picture definition SMPTE RP187, ITU-R. BT.470

Aspect ratio preservation SMPTE RP199-1999, SMPTE RP221

Color space conversion HD: ITU-R. BT.709

SD: ITU-R. BT.601

network-electronics.com | 8

DWC-HD Rev. 2

See also ITU-R. BT.1361 for more information

Video switch point SMPTE RP168 (tri-level), SMPTE 170M, ITU-R. BT.470

definition and sync

AES AES3-1996

Optical SMPTE 297M, SMPTE 292M

EDH Compliant to SMPTE RP165

Video Payload SMPTE 352M-2002

Identification

Other

Power consumption 5V – 5.3W (4.9W without optical receiver)

15V – 2.55W

-15V – 0.7W

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DWC-HD Rev. 2

3 Description

3.1 Data path

The HD/SD-SDI input selected from the optical or electrical input is equalized, re-clocked and

de-serialized and transferred to a processing unit (FPGA). In the FPGA the signal is sent

through a de-glitcher that cleans up erroneous video lines, for instance due to switching.

After the de-glitcher the video is sent to the Audio de-embedders, where audio is split from

the video.

3.1.1 Audio data path

The 16 audio channels coming out of the de-embedder are bundled in pairs and sent to an

audio store buffer. After a user specified delay the audio is fetched from the audio store

buffer and sent to an Audio Cross Point. The 10 audio outputs from the Audio Cross Point

can be any pair of audio channels de-embedded from the incoming video stream, a

generated 1 kHz sine, or a generated black sound (a legal audio stream with silence only).

As part of the audio cross point, missing output pairs can be replaced with generated fallback

signals. From the cross point outputs each stereo pair enters an Audio Processing Block

where channels can be processed or rearranged within each channel pair. Finally, eight

stereo pairs are routed to the Audio Embedder and the two remaining pairs are sent to the

audio DAC and the AES out, respectively.

3.1.2 When down-converting HD video

The video is routed to a Scaling block and the resulting SD video is passed to a Frame

synchronizer block. If video is missing, an internal video generator can be switched in as a

fallback source. The video then passes through a Video processing block with an integrated

Legalizer, before entering an EDH processing block where the user can select to insert

updated EDH flags. Although audio is re-embedded before the video processing block, the

video processing and EDH processing blocks will not manipulate the audio data.

After passing the EDH block, the video stream with embedded audio is sent in parallel out of

the FPGA and into a serializer that re-clocks the data and sends the SDI to a buffered output

switch.

The buffered output switch can be viewed as 3 simple switches, each selecting between the

equalized and re-clocked output (Through mode) and the down-converted output (Processed

mode). The output of the first two switches are sent to two paired (inverting and non-

inverting) digital outputs, whereas output of the third switch is sent to the onboard video

DAC.

3.1.3 When frame synchronizing SD video

The video data path when operating as an SD frame synchronizer is conceptually the same

as when down-converting, except that the Scaling block is not needed, placing the Frame

synchronizer block directly after the de-glitcher.

network-electronics.com | 10

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