Norsk Data ND-100 Manuale utente

Reference

Manual

ND-06.014.02

NORSK

DATA

A.S

3%.:

we...

vvmoe

D-100

Reference

Manual

ND-06.014.02

TICE

"""“l"h‘e'"information

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Notes

ECOND

PRINTING

ND-100

Reference

Manual

ND-06.014.02

:::

:::::::.

NORSK

DATA

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EE§°3§EE§

535:3553

S‘s‘ﬂ,‘

iaé’xN‘gnﬁiZdebe'ggé'd

...

.......

Manuals

can

updated

two

ways,

new

versions

and

revisions.

New

versions

consist

complete

new

manual

which

replaces

the

old

manual.

New

versions

incorporate

all

revisions

since

the

version.

Revisions

consist

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single

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merged

into

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manual

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user,

each

revised

page

being

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out

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manual.

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the

local

office

(in

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to:

Documentation

Department

Norsk

Data

A.S

PO.

Box

Lindeberg

gérd

Oslo

Section:

1.1

1.2

1.2.1

1.2.2

1.2.2.1

1.2.3

1.2.3.1

1.2.3.2

1.2.3.3

1.2.3.4

1.3

1.4

1.5

1.5.1

1.5.2

1.5.3

1.6

1.6.1

1.6.2

1.7

1.8

1.8.1

1.8.2

1.8.3

2.1

TABLE

CONTENTS

+ +

Page:

INTRODUCTION

ND-100

.................................................

1—1

General

Characteristics

....................................................

1—"1

ND-100

Functional

Modules

.............................................

1L3

General

.......................................................................

1—3

ND-100

Central

Processing

Unit

(CPU)

Module

.........

1—5

CPU

Characteristics

..............................................

1—6

ND-100

Architecture

...................................................

-—7

General

..................................................................

1—7

ND-100

Configuration

Examples

...........................

1—8

Multiprocessor

Systems

.......................................

—9

Remote

Operation

.................................................

—10

The

Interrupt

System

.......................................................

—11

The

Memory

Management

System

.................................

1—12

The

Memory

System

........................................................

—-13

Main

Memory

.............................................................

1—1’3

Cache

Memory

...........................................................

1—13

Multiport

Memory

.......................................................

1—13

The

Input/Output

System

................................................

1—14

Programmed

Input/Output

—

PIO

.............................

1—14

Direct

Memory

Access

—

DMA

.................................

1—14

ND-100

Peripheral

Equipment

.........................................

1—15

ND-100

Software

..............................................................

1—16

The

Operating

System

................................................

1—16

Supporting

Software

..................................................

1—17

Distributed

Data

Processing

.......................................

1—17

SYSTEM

DESCRIPTION

........................................................

2—1

Central

Processor

.............................................................

2-1

ND-06.014.02

Section:

Page:

2.1.1

General

......................................................................

2—1

2.1.2

Internal

Communication

............................................

2—3

2.1.3

The

Address

Arithmetic

..............................................

2—3

2.1.4

Instruction

Fetch

.......................................................

2—3

2.1.5

Prefetch

.....................................................................

2—3

2.1.6

Instruction

Execution

.................................................

2—4

2.1.7

Main

Arithmetic

..........................................................

2—4

2.1.8

The

File

.........................................................

2—6

2.1.9

Status

Indicators

.......................................................

2—8

2.2

The

Interrupt

System

.......................................................

2—10

2.2.1

General

......................................................................

2—10

2.2.2

Functional

Description

..............................................

2—12

2.2.3

The

External

Interrupt

System

...................................

2—14

2.2.4

The

Internal

Interrupt

System

....................................

2—16

2.2.4.1

The

IIC

and

IIE

Registers

.............................

........

2—17

2.2.4.2

Internal

Hardware

Status

Interrupts

....................

2—18

2.2.4.3

Reset

the

IIC

.....................................

2—20

2.2.5

Programmming

Control

the

Interrupt

System

......

2—21

2.2.5.1

Programmming

the

PID

and

PIE

Registers

.........

2—21

2.2.5.2

The

WAIT,

ION

and

IOF

Instruction

.....................

2—22

2.2.5.3

The

Level

PVL

........................

2—22

2.2.5.4

Vectored

Interrupts

and

the

IDENT

Instructions

.2—23

—2.2.6

Initializing

the

Interrupt

System

...........................

2—24

2.3

The

Memory

Management

System

.................................

2—25

2.3.1

General

......................................................................

2—25

2.3.2

Memory

Management

Architecture

..........................

2—26

2.3.3

The

Paging

System

.....................................................

2—28

2.3.4

The

Shadow

Memory

.................................................

2—30

2.3.5

The

Page

Tables

.......................................................

2—32

2.3.5.1

Page

Used

and

Written

Page

..........................

2—34

2.3.5.2

Page

Table

Selection

...........................................

2—34

2.3.6

Memory

Protection

System

......................................

2—35

2.3.6.1

Page

Protection

System

.......................................

2—35

2.3.6.2

Ring

Protection

System

.......................................

2—37

2.3.7

Privileged

Instructions

...............................................

2—39

2.3.8

Memory

Management

Control

and

Status

...............

2—40

ND-06.014.02

Section:

2.3.8.1

2.3.8.2

2.3.8.3

2.3.9

2.4

2.4.1

2.4.2

2.4.2.1

2.4.2.2

2.4.2.3

2.4.2.4

2.4.3

2.4.4

2.4.4.1

2.4.4.2

2.4.5

2.4.5.1

2.21.5.2

2.4.6

2.4.6.1

2.4.6.2

2.4.6.3

2.4.6.3.1

2.4.6.3.2

2.5

2.5.1

2.5.2

2.5.3

2.5.4

2.5.5

2.5.6

2.5.6.1

2.5.6.2

2.5.6.3

2.5.7

vii

Page:

The

PON

and

POF

Instructions

.............................

2—40

Paging

Control

Registers

......................................

2—41

Paging

Status

.........................................

2—42

The

SEX

and

REX

Instructions

...................................

2—43

ND-100

Memory

System

..................................................

2—44

General

......................................................................

2—44

ND-100

Memory

Architecture

....................................

2—46

Local

(Main)

Memory

............................................

2—47

Memory

Module

Placement

Eurobus

...............

2—47

The

Position

Code

.................................................

2—47

The

Thumbwheel

Setting

......................................

2—48

Memory

Error

Correction

...........................................

2—50

Memory

Control

and

Status

.......................................

2—52

Error

Correction

Control

(ECCR)

............

2—52

Memory

Status

Regsiters

(PEA

and

PES)

............

2—53

Multiport

Memory

.......................................................

2—54

Big

Multiport

Memory

(BMPM)

............................

2—54

Multiport

Memory

(MPM4)

................................

2—54

Cache

Memory

...........................................................

2—55

Cache

Memory

Architecture

.................................

2—55

Cache

Memory

Organization

................................

2—56

Cache

Control

and

Status

.........

...........................

2—58

Cache

Control

..................................................

2—58

Cache

Status

.....................................

2—-59

ND-100

Input/Output

System

..........................................

2—60

General

.......................................................................

2—60

ND-100

l/O

Architecture

.............................................

2—61

ND‘100

Card

Crate

—

Physical

Layout

......................

2—62

The

ND-100

Bus

..........................................................

2—65

ND-1OO

l/O

System

Function

Description

..................

2—66

Programmed

Input/Output

—

PIO

.............................

2—67

The

Input/Output

Instruction

—-

lOX

....................

2—67

Interface

Channels

and

Registers

.........................

2—68

Control

and

Status

.................................

2—7‘1

Direct

Memory

Access

(DMA)

...................................

2—62

ND-06.014.02

Section:

2.5.7.1

2.5.7.2

2.5.7.2.1

2.5.7.2.2

2.5.7.2.3

2.5.7.2.4

2.5.8

2.5.8.1

2.5.8.2

2.5.8.3

2.5.9

2.5.9.1

2.5.9.2

2.6

2.6.1

2.6.2

3.1

3.1.1

3.1.2

3.1.2.1

3.1.2.2

3.1.2.3

3.1.2.4

3.1.2.5

3.1.2.6

3.2

3.2.1

3.2.1.1

3.2.1.2

3.2.1.3

viii

Page:

General

..................................................................

2—72

DMA

Controller

Operation

....................................

2—72

Initialization

...........................................................

2—73

Transfer

.................................................................

2—73

Termination

and

Status

Check

..............................

2—73

General

Considerations

.........................................

2—74

The

I/O

System

and

the

Interrupt

System

................

2—75

General

..................................................................

2—75

Interrupt

Level

Usage

............................................

2—75

Device

Interrupt

Identification

..............................

2—76

Programming

Specifications

for

|/O

Device

the

CPU

Board

.......................................................

2—76

The

Real-time

Clock

..............................................

2-77

The

Current

Loop

Interface

...................................

2—77

ND-IOO

Bus

Extender

(BEX)

............................................

2—79

General

......................................................................

2—79

Bus

Extender

Architecture

.........................................

2—79

ND-IOO

INSTRUCTIONS

.......................................................

3—1

Introduction

the

Instruction

Repertoire

......................

3—1

General

.......................................................................

3—1

General

.......................................................................

3—1

Instruction

and

Data

Formats

....................................

3—3

Single

Bit

...............................................................

3—3

Bit

Byte

...............................................................

3—4

Bit

Word

...........................................................

3—4

Bit

Double

Word

...............................................

3—5

Bit

Floating

Point

Word

....................................

3—6

Bit

Floating

Point

Word

....................................

3—7

The

Instruction

Repertoire

...............................................

3—9

Memory

Reference

Instructions

.................................

3—9

Addressing

Structure

............................................

3—9

Store

Instructions

..................................................

3—18

Load

Instructions

...................................................

3—20

ND-06.014.02

Section:

3.2.1.4

3.2.1.5

3.2.1.6

3.2.1.7

3.2.2

3.2.2.1

3.2.2.1.2

3.2.2.2

3.2.2.3

3.2.2.3.1

3.2.2.3.2

3.2.2.4

3.2.2.5

3.2.2.6

3.2.2.6.1

3.2.2.6.2

3.2.2.6.3

3.2.3

3.2.3.1

3.3

3.3.1

3.3.2

3.3.3

3.3.4

3.3.5

3.3.5.1

3.3.6

3.3.6.1

3.3.6.2

3.3.6.3

3.3.7

3.3.8

3.3.9

3.3.10

Page:

Arithmetical

and

Logical

Instructions

...................

3—21

Sequencing

Instructions

.......................................

3—24

Byte

Instructions

...................................................

3—26

Extended

BYTE-instructions

..................................

3—27

Instructions

..................................................

3—30

Floating

Point

Conversion

Instructions

.........

.......

3—30

Standard

Bit

Floating

Point

Conversion

.....

3—30

Optional

Bit

Floating

Point

Conversion

.......

3—32

Shift

Instructions

...................................................

3—33

Operations

..............................................

3—36

ROP

—

Operation

Instructions

.........

3—38

Extended

Operation

Instructions

......

3—45

Skip

Instructions

...................................................

3—47

Argument

Instructions

..........................................

3—50

Bit

Operation

Instructions

.....................................

3—53

Bit

Skip

Instructions

........................................

3—54

Bit

Set

Instructions

..........................................

3—54

One

Bit

Accumulator

Instructions

...................

3—55

System

Control

Instructions

.......................................

3-56

Monitor

Call

Instruction

...........................

3—56

Privileged

Instructions

....................................................

3—57

General

......................................................................

3—57

Block

Instructions

........................................

3—57

Inter-level

Instructions

.................................

3—59

Accumulator

Transfer

Instructions

.............................

3-60

Input/Output

Control

Instructions

..............................

3—63

Extension

the

Device

Address

...........

3—64

System

Control

Instructions

.......................................

34-64

Interrupt

Control

Instructions

...............................

3—65

Memory

Managementlﬂontrol

Instructions

..........

3—68

Wait

Give

Priority

........................................

3—70

Examine

and

Deposit

..................................................

3—71

Load

Writeable

Control

Store

....................................

3—72

Customer

Specified

Instructions

................................

3—73

Physical

Memory

Read/Write

Instructions

................

3—74

ND-06.014.02

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