Quatech DS-302 Manuale utente

WARRANTY INFORMATION

Quatech Inc. warrants the DS-202/DS-302

to be free of defects for one (1)year from the

date of purchase. Quatech Inc. will repair or replace

any board that fails to perform under normal operating

conditions and in accordance with the procedures

outlined in this document during the warranty period.

Any damage that results from improper installation,

operation, or general misuse voids all warranty rights.

Although every attempt has been made to guarantee

the accuracy of this manual, Quatech Inc. assumes no

liability for damages resulting from errors in this

document. Quatech Inc. reserves the right to edit or

append to this document at any time without notice.

Please complete the following information and

retain for your records. Have this information

available when requesting warranty service.

DATE OF PURCHASE:

MODEL NUMBER: DS-202/DS-302

PRODUCT DESCRIPTION: DUAL CHANNEL RS-422/RS-485

ASYNCHRONOUS COMMUNICATION BOARD

SERIAL NUMBER:

IBMTM, PC/XTTM, PC/ATTM, and PS/2TM are trademarks of

International Business Machines.

TABLE OF CONTENTS

WARRANTY INFORMATION . . . . . . . . . . . . i

LIST OF FIGURES . . . . . . . . . . . . . iii

I. INTRODUCTION . . . . . . . . . . . . . . . . 1

II. BOARD DESCRIPTION . . . . . . . . . . . . . 1

III. 16450/16550*FUNCTIONAL DESCRIPTION . . . . 1

INTERRUPT ENABLE REGISTER . . . . . . . . 4

INTERRUPT IDENTIFICATION REGISTER . . . . 5

FIFO CONTROL REGISTER *. . . . . . . . . 7

LINE CONTROL REGISTER . . . . . . . . . . 8

MODEM CONTROL REGISTER . . . . . . . . . 10

LINE STATUS REGISTER . . . . . . . . . . 11

MODEM STATUS REGISTER . . . . . . . . . . 13

SCRATCHPAD REGISTER . . . . . . . . . . . 14

FIFO INTERRUPT MODE OPERATION *. . . . . 14

IV. BAUD RATE SELECTION . . . . . . . . . . . . 14

V. ADDRESSING . . . . . . . . . . . . . . . . . 16

VI. INTERRUPTS . . . . . . . . . . . . . . . . . 18

VII. OUTPUT CONFIGURATIONS . . . . . . . . . . . 19

VIII. EXTERNAL CONNECTIONS . . . . . . . . . . . . 23

IX. INSTALLATION . . . . . . . . . . . . . . . . 24

X. SPECIFICATIONS . . . . . . . . . . . . . . . 24

*with optional 16550.

INTRODUCTION

LIST OF FIGURES

Figure 1. DS-202/DS-302 board layout . . . . . . 2

Figure 2. 16450/16550*internal registers . . . 3

Figure 3. Interrupt source identification . . . 6

Figure 4. FIFO receiver trigger levels*. . . . 7

Figure 5. Parity options . . . . . . . . . . . . 9

Figure 6. Word length and stop bit options . . . 9

Figure 7. Input clock frequency selections . . . 15

Figure 8. Divisor latch options . . . . . . . . 15

Figure 9. Address selection switches . . . . . . 16

Figure 10. Address selection examples . . . . . . 17

Figure 11. Channel enable/disable selection . . . 17

Figure 12. System interrupt connection . . . . . 18

Figure 13. Interrupt mode selection . . . . . . . 18

Figure 14. Output control block diagram . . . . . 19

Figure 15. Auxiliary channel jumper definition . 20

Figure 16. Auxiliary channel signal selection . . 21

Figure 17. Half duplex control jumper . . . . . . 21

Figure 18. Output connector definition . . . . . 23

*with optional 16550.

iii

INTRODUCTION

I. INTRODUCTION

The DS-202 is a dual channel RS-422 asynchronous

serial communications adapter for systems implementing

an ISA compatible I/O bus. Data is communicated

through two shielded D-9 connectors which provide

greater shielding from environmental noise. The DS-302

is an RS-485 version of the adapter.

The serial interface is implemented with a pair of

16450 Asynchronous Communication Elements (ACEs). The

16450 is compatible with the 8250 ACE found in the

original IBM PC/XT models. The optional 16550 ACE

provides an additional FIFO mode of operation which

reduces CPU overhead at higher data rates.

The DS-202 / DS-302 allows independent addressing

of each channel through a pair of address decode

switches (SW1 and SW2). These switches allow each

channel to be addressed in the I/O address range 0000H

through 07FFH. Each channel is also capable of

selecting and / or sharing one of six possible

interrupt request lines (IRQ 2,3,4,5,6,7).

II. BOARD DESCRIPTION

A component diagram of the DS-202 / DS-302 showing

the locations of the 16450 ACEs, configuration jumpers,

address selection switches, and output connectors is

shown in figure 1. The first communication channel is

controlled by the ACE labeled U7, switch SW1 for

addressing, jumpers J2 and J5 for interrupt request

selection, jumpers J7 and J8 for output signal control,

and is output through connector CN1. The second

channel is controlled by the ACE labeled U8, switch SW2

for addressing, jumpers J3 and J6 for interrupt request

selection, jumpers J8 and J10 for output signal

control, and is output through connector CN2.

III. 16450/16550FUNCTIONAL DESCRIPTION

The 16450 is an improved specification version of

the 8250 Asynchronous Communications Element (ACE)

found in the original IBM PC and PC/XT systems and is

functionally equivalent to the 8250. This ACE performs

serial-to-parallel conversion on received data and

parallel-to-serial conversion on data output from the

CPU.

iii

Figure 1. DS-202 / DS-302 component layout.

FUNCTIONAL DESCRIPTION

Designed to be compatible with the 16450, the

16550 ACE enters character mode on reset and in this

mode appears as a 16450 to application software. An

additional mode, FIFO mode, can be invoked through

software to reduce CPU overhead by providing two 16-

byte FIFOs (one transmit, one receive) to buffer data

and reduce the number of interrupts issued to the CPU.

Other features of the 16450/16550 include:

Programmable baud rate, character length, parity,

and number of stop bits.

Automatic addition and removal of start, stop, and

parity bits.

Independent and prioritized transmit, receive and

status interrupts.

The following pages provide a brief summary of the

internal registers available within the 16450 and 16550

ACEs. The registers are addressed as shown in figure 2

below. Registers and functions specific to the

optional 16550 are indicated with an asterisk (*).

+---------------+------------------------------+

| DLAB A2 A1 A0 | REGISTER DESCRIPTION |

+---------------+------------------------------+

| 0 0 0 0 | Receive buffer (read only) |

| | Transmit holding register |

| | (writeonly) |

| 0 0 0 1 | Interrupt enable |

| x 0 1 0 | Interrupt identification |

| | (read only) |

| | FIFO control*(write only) |

| x 0 1 1 | Line control |

| x 1 0 0 | MODEM control |

| x 1 0 1 | Line status |

| x 1 1 0 | MODEM status |

| x 1 1 1 | Scratch |

| 1 0 0 0 | Divisor latch (LSB) |

| 1 0 0 1 | Divisor latch (MSB) |

+---------------+------------------------------+

Figure 2. Internal register map for 16450/16550 ACE.

DLAB is accessed through the Line Control

*with optional 16550.

FUNCTIONAL DESCRIPTION

INTERRUPT ENABLE REGISTER

+-------+

D7 | 0 |

+-------+

D6 | 0 |

+-------+

D5 | 0 |

+-------+

D4 | 0 |

+-------+

D3 | EDSSI |----- MODEM status

+-------+

D2 | ELSI |----- Receiver line status

+-------+

D1 | ETBEI |----- Transmitter holding register empty

+-------+

D0 | ERBFI |----- Received data available

+-------+

EDSSI - MODEM Status Interrupt:

When set (logic 1), enables interrupts on clear

to send, data set ready, ring indicator, and

data carrier detect.

ELSI - Receiver Line Status Interrupt:

When set (logic 1), enables interrupts on

overrun, parity, framing errors, and break

indication.

ETBEI - Transmitter Holding Register Empty Interrupt:

When set (logic 1), enables interrupts on

transmitter register empty.

ERBFI - Received Data Available Interrupt:

When set (logic 1), enables interrupts on

received data available or the receiver FIFO

trigger level*.

*with optional 16550.

FUNCTION

AL DESCRIPTION

INTERRUPT IDENTIFICATION REGISTER

+------+

D7 | FFE |--+

+------+ +-- FIFO enable *

D6 | FFE |--+

+------+

D5 | 0 |

+------+

D4 | 0 |

+------+

D3 | IID2 |--+

+------+ |

D2 | IID1 | +-- Interrupt identification

+------+ |

D1 | IID0 |--+

+------+

D0 | IP |----- Interrupt pending

+------+

FFE - FIFO Enable:*

When logic 1, indicates FIFO mode enabled.

IIDx - Interrupt Identification:

Indicates highest priority interrupt pending if

any. See IP and figure 3. NOTE: IID2 is

always a logic 0 in the 16450 and in the 16550

character mode.

IP - Interrupt Pending:

When logic 0, indicates that an interrupt is

pending and the contents of the interrupt

identification register may be used to determine

the interrupt source. See IIDx and figure 3.

*with optional 16550.

FUNCTIONAL DESCRIPTION

+--------------------+----------+----------------------+

| IID2 IID1 IID0 IP | Priority | Interrupt Type |

+--------------------+----------+----------------------+

| x x x 1 | N/A | None |

| 0 1 1 0 | Highest | Receiver Line Status |

| 0 1 0 0 | Second | Received Data Ready |

| 1 1 0 0 | Second | Character Timeout |

| | | (FIFO mode only)*|

| 0 0 1 0 | Third | Transmitter Holding |

| | | Register Empty |

| 0 0 0 0 | Fourth | MODEM Status |

+--------------------+----------+----------------------+

Figure 3. Interrupt Identification bit definitions.

Receiver Line Status:

Indicates overrun, parity, framing errors or

break interrupts. The interrupt is cleared by

reading the line status register.

Received Data Ready:

Indicates receive data available. The interrupt

is cleared by reading the receive buffer.

FIFO mode:*

Indicates the receiver FIFO trigger level has

been reached. The interrupt is reset when the

FIFO drops below the the trigger level.

Character Timeout: (FIFO mode only)*

Indicates no characters have been removed from

or input to the receiver FIFO for the last four

character times and there is at least one

character in the receiver FIFO. The interrupt

is cleared by reading the receiver FIFO.

Transmitter Holding Register Empty:

Indicates the transmitter holding register is

empty. The interrupt is cleared by reading the

interrupt identification register or writing to

the transmitter holding register.

MODEM Status:

Indicates clear to send, data set ready, ring

indicator, or data carrier detect have changed

state. The interrupt is cleared by reading the

MODEM status register.

*with optional 16550.

FUNCTION

AL DESCRIPTION

FIFO CONTROL REGISTER *

+------+

D7 | RXT1 |--+

+------+ +-- Receiver trigger *

D6 | RXT0 |--+

+------+

D5 | x |--+

+------+ +-- Reserved

D4 | x |--+

+------+

D3 | DMAM |----- DMA mode select *

+------+

D2 | XRST |----- Transmit FIFO reset *

+------+

D1 | RRST |----- Receive FIFO reset *

+------+

D0 | FE |----- FIFO enable *

+------+

RXTx - Receiver FIFO Trigger Level:*

Determines the trigger level for the FIFO

interrupt as given in figure 4 below.

+-----------+-----------------------+

| | RCVR FIFO |

| RXT1 RXT0 | Trigger level (bytes) |

+-----------+-----------------------+

| 0 0 | 1 |

| 0 1 | 4 |

| 1 0 | 8 |

| 1 1 | 14 |

+-----------+-----------------------+

Figure 4. FIFO trigger levels.

DMAM - DMA Mode Select:*

When set (logic 1), RxRDY and TxRDY change from

mode 0 to mode 1. (DMA mode is not supported by

the DS-202 / DS-302.)

XRST - Transmit FIFO Reset:*

When set (logic 1), all bytes in the transmitter

FIFO are cleared and the counter is reset. The

shift register is not cleared. XRST is self-

clearing.

*with optional 16550.

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