Renesas REJ06B0732-0100 Istruzioni per l'installazione e il funzionamento

APPLICATION NOTE

REJ06B0732-0100/Rev.1.00 March 2008 Page 1 of 13

SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

Introduction

This application note describes the operation of the DMAC, and is intended for reference to help in the design of user

software.

Target Device

SH7211

Contents

1. Introduction ....................................................................................................................................... 2

2. Description of Sample Application.................................................................................................... 3

3. Documents of Reference................................................................................................................ 11

SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

REJ06B0732-0100/Rev.1.00 March 2008 Page 2 of 13

1. Introduction

1.1 Specification

•DMAC channel 0 is used.

•Auto-request mode is used as the interrupt source for activating DMA transfer.

•Cycle-stealing mode is used as the bus mode.

1.2 Used Module

•Direct memory access controller (DMAC channel 0)

1.3 Applicable Conditions

•Microcontroller: SH7211

•Operating Frequency: Internal clock 160 MHz

Bus clock 40 MHz

Peripheral clock 40 MHz

•C Compiler: SuperH RISC engine family C/C++ compiler package Ver.9.01,

from Renesas Technology

SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

REJ06B0732-0100/Rev.1.00 March 2008 Page 3 of 13

2. Description of Sample Application

In this sample application, the direct memory access controller (DMAC) is set to auto request mode to transfer 512-

Kbtyte data stored in the on-chip RAM to another address.

2.1 Operation of Modules Used

When a DMA transfer request is made, the DMAC starts to transfer data in accordance with the priority order of

channels and continues the transfer operation until the transfer end condition is met. Transfer requests for the DMAC

are of three kinds: auto requests, external requests, and on-chip peripheral module requests. The bus mode is selectable

as burst mode or cycle-stealing mode.

For details on the DMAC, refer to the section on the direct memory access controller in the SH7211 Group Hardware

Manual.

An overview of the DMAC is given in table 1. Examples of DMA transfer in cycle-stealing mode and burst mode are

shown in figures 1 and 2, respectively. In addition, a block diagram of the DMAC is shown in figure 3.

Table 1 Overview of DMAC

Item Description

Number of channels 8 (CH0 to CH7)

Only 4 (CH0 to CH3) can receive external requests.

Address space 4 Gbytes

Length of transfer data Byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword ×4)

Maximum transfer count 16,777,216 (24 bits) transfers

Address mode Single address mode and dual address mode

Transfer request External request, on-chip peripheral module request, and auto request

(SCIF: 8 sources, IIC3: two sources, A/D converter: one source, MTU2:

five sources, CMT: two sources)

Bus mode Cycle-stealing mode (normal mode and intermittent mode) and burst

mode

Priority level Channel priority fixed mode and round-robin mode

Interrupt request An interrupt request to the CPU is made when half or all of a transfer

process is completed.

External request detection DREQ input low/high level detection, rising/falling edge detection

Transfer request acknowledge

signal/transfer end signal Active levels for DACK and TEND can be set independently

SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

REJ06B0732-0100/Rev.1.00 March 2008 Page 4 of 13

DREQ

Bus mastership returned to CPU once

Bus cycle

WriteRead WriteRead

CPU CPU CPU DMAC DMAC DMAC DMAC CPUCPU

In the normal mode of cycle stealing, bus mastership is given to another bus master after each DMA

transfer of one transfer unit (byte, word, longword, or 16-byte unit). When a subsequent transfer

request occurs, bus mastership is obtained from the other bus master and transfer proceeds for one

transfer unit. When that transfer ends, the bus mastership is passed to another bus master. This is

repeated until the transfer end condition is satisfied.

The cycle-stealing normal mode can be used in transfer across any interval, regardless of the

requesting source, source, and destination of the transfer.

Figure 1 DMA Transfer Example in Cycle-Stealing Normal Mode

(Dual Address, DREQ Low Level Detection)

DREQ

CPU CPU CPU DMAC DMAC DMAC DMAC CPUCPU

Bus cycle

Read Write Read Write

In burst mode, once the DMAC has obtained bus mastership, it continues to perform transfer without

releasing the bus until the transfer end condition is satisfied. In external mode, however, when the DREQ

signal is being level-detected and changes to the non-active level, even if the tranfer end condition has not

been satisfied, bus mastership is passed to another bus master on completion of the DMA transfer request

for which the request has already been accepted.

Figure 2 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection)

SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

REJ06B0732-0100/Rev.1.00 March 2008 Page 5 of 13

DMATCR_n

SAR_n

CHCR_n

DAR_n

DMAOR

DMARS0 to DMARS3

HEIn

DACK0 to DACK3,

TEND0, TEND1

DEIn

RDMATCR_n

RSAR_n

RDAR_n

On-chip

memory

On-chip

peripheral

module

DMA transfer

request signal

DMA transfer acknowledge signal

Interrupt controller

External ROM

External RAM

External device

(memory mapped)

External device

(with acknowledge)

DREQ0 to DREQ3

Peripheral bus

Internal bus

DMAC module

Iteration

control

Start-up

control

Request

priority

control

Bus

interface

Bus state

controller

[Legend]

RDMATCR: DMA reload transfer count register CHCR: DMA channel control register

DMATCR: DMA transfer count register DMAOR: DMA operation register

RSAR: DMA reload source address register DMARS0 to DMARS3: DMA extension resource selectors 0 to 3

SAR: DMA source address register HEIn: DMA transfer half-end interrupt request to the CPU

RDAR: DMA reload destination address register DEIn: DMA transfer end interrupt request to the CPU

DAR: DMA destination address register n: 0, 1, 2, 3, 4, 5, 6, 7

Figure 3 Block Diagram of DMAC

SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

REJ06B0732-0100/Rev.1.00 March 2008 Page 6 of 13

2.2 Operational Description of Sample Program

The settings of the DMAC for the sample program are listed in table 4. Also, the operation of the sample program is

illustrated in figure 4.

Table 4 Settings of DMAC

DMA transfer condition Auto request mode

Channel CH0

Length of transfer data 4 bytes

Maximum transfer count 128 transfers (128 ×data length of 4 bytes = 512-byte data)

Address mode Dual address mode

Bus mode Cycle-stealing mode

Priority level Channel priority level fixed mode

Interrupt request Disable an interrupt request to the CPU at the end of a transfer

DMAC H'0xFFF81000

H'0xFFF82000

DAR

SAR

Transfer source

address

On-chip RAM

DMA transfer

512-byte data

Transfer

destination

address

[Legend]

SAR:Source address register

DAR:Destination address register

Figure 4 Operation of Sample Program

SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

REJ06B0732-0100/Rev.1.00 March 2008 Page 7 of 13

2.3 Procedure for Setting Modules

This section describes the procedure for making initial settings when the DMAC is to be used to transfer data between

locations within the on-chip RAM. Auto request mode is used for the transfer requests.

By default, the on-chip peripheral modules of this MCU are in module standby mode. Whenever any of these modules

is to be used, be sure to take it out of module standby mode before making the initial settings. Although processing to

delete the end of DMA transfer is typically handled by interrupts, polling is used in this sample application. A

flowchart of the sample program is shown in figure 5. In addition, a flowchart of DMAC initialization is shown in

figure 6.

For details on registers, refer to the SH7211 Group Hardware Manual.

main

DMAC0.CHCR.BIT.DE = 1

DMAC0.CHCR.BIT.DE = 0

STB.CR2.BIT._DMAC = 0

END

[3]

[4]

[5]

[1]

[2]

Yes

DMAC_init

512-byte Initialization

completed?

Transfer completed?

[1] Cancel module standby mode

Activate the DMAC

[2] Initialize the DMAC (channel 0)

[3] Initialize the transfer destination

Clear a 512-byte area to 0

[4] Enable DMA transfer

Set DMA enable flag

[5] Perform DMA transfer end processing

Disable DMA transfer after confirmation

of the tranfer end.

*In this sample application, sleep processing is performed after the main routine is complete.

Figure 5 Flowchart of Sample Program

SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

REJ06B0732-0100/Rev.1.00 March 2008 Page 8 of 13

DMAC_init

END

[3]

[4]

[5]

[6]

[1]

[2]

[1] Disable DMA transfer

Set the DE (DMA enable) bit to 0

Disable DMA transfer

[2] Set the DMA transfer source address (SAR_0)

Specify the DMA transfer source address

[3] Set the DMA transfer destination address (DAR_0)

Specify the DMA transfer destination address

[4] Specify the DMA transfer count (DMATCR_0)

Set the DMA transfer count to 128

[5] Set the channel control register (CHCR_0)

Set TC to B’1: transfer data for the count specified in DMATCR

Set RLD to B’0: disable the reload function

Set RS[3:0] (resource selector) to B’0100: auto request

Set DM[1:0] to B’01: increment the destination address

Set SM[1:0] to B’00: fix the source address

Set TB to B’0: cycle steal mode

Set IE to B’0: disable interrupts

[6] Set the DMA operation register (DMAOR)

Read from the AE and MNIF bits and clear them to 0

Clear the address error flag

Set the DME bit to 1 after clearing the flags

Enable DMA transfer on all the channels

Set DMA channel control register

(CHCR_0)

Set DMA source address register

(SAR_0)

Set DMA destination address

Set DMA transfer count register

(DMATCR_0)

Set DMA channel control register

(CHCR_0)

Set DMA operation register

(DMAOR)

Figure 6 Flowchart of Initializing DMAC

SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

REJ06B0732-0100/Rev.1.00 March 2008 Page 9 of 13

2.4 Register Settings for Sample Program

2.4.1 Clock Pulse Generator (CPG)

The settings of the clock pulse generator for the sample program are described in table 5.

Table 5 Settings of Clock Pulse Generator

Frequency control

STC[1:0] = “B’00”: frequency multiplication

ratio of PLL circuit ×1

IFC[2:0] = “B’000”: internal clock ×1

PFC[2:0] = “B’011”: peripheral clock ×1/4

2.4.2 Standby Control Register

The settings of the standby control register for the sample program are described in table 6.

Table 6 Settings of Standby Control Register

Standby control

SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

REJ06B0732-0100/Rev.1.00 March 2008 Page 10 of 13

2.4.3 Direct Memory Access Controller (DMAC)

The settings of DMAC registers for the sample program are described in table 7.

Table 7 Settings of DMAC Registers

DMA source address

DMA destination address

DMA transfer count

128 transfers

H’0000 0000 Before DMA initialization

DE = “B’0”: disables DMA transfer

H’8000 4410 DMA initialization

TC = “B’1”: transfers data for the count

specified in DMATCR for each transfer

request

DM[1:0] = “B’01”: increments the destination

address

SM[1:0] = “B’00”: fixes the source address

RS[3:0] = “B’0100”: auto request

TB = “B’0”: cycle-stealing mode

TS[1:0] = “B’10”: longword (4 bytes) unit

IE = “B’0”: disables interrupt requests

DE = “B’0”: disables DMA transfer

H’8000 4411 When enabling DMA transfer

DE = “B’1”: enables DMA transfer

DMA channel control

H’8000 4410 When disabling DMA transfer

DE = “B’0”: disables DMA transfer

DMA operation register

(DMAOR) H’FFFE1200 H’0000 0001 DME = “B’1”: enables DMA transfer on all the

channels

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