Contents
1The connector specifications......................................................................................................................................... 6
1.1. RJ45 connector .............................................................................................................................................................. 6
1.2. Power/IO connector........................................................................................................................................................ 7
1.2.1 Input signal ............................................................................................................................................................... 8
1.2.2 Output signals........................................................................................................................................................... 8
1.3. DC IRIS lens connector.................................................................................................................................................. 9
2I/O circuits ...................................................................................................................................................................... 10
2.1 Input circuit.................................................................................................................................................................... 10
2.2 Output circuit ................................................................................................................................................................. 12
3User configurable FPGA (XILINX) ................................................................................................................................ 13
3.1 User configurable FPGA (XILINX) information.........................................................................................................13
3.1.1 Device information............................................................................................................................................. 13
3.1.2 User program examples....................................................................................................................................13
3.2 Block diagram and explanation ................................................................................................................................ 14
3.2.1 Block Diagram................................................................................................................................................... 14
3.2.2 Explanations of data flows ................................................................................................................................15
3.2.3 Important design consideration of data timing and handling............................................................................. 24
3.3 Connection information between the devices .......................................................................................................... 25
3.3.1 Connection between the user configurable FPGA (XILINX) and the Sentech FPGA.......................................25
3.3.2 Connection between user configurable FPGA (XILINX) and DDR2 ................................................................. 27
3.3.3 Connection between the user configurable FPGA (XILINX) and the EEPROM ...............................................28
3.4 Development guideline.............................................................................................................................................29
3.4.1 Module and constraints files..............................................................................................................................29
3.4.2 Important design cautions.................................................................................................................................29
3.4.3 Notice for use DDR2 memory...........................................................................................................................30
3.4.4 Recommend the image data handle between the Sentech FPGA and the user configurable FPGA............... 31
3.4.5 Copy guard function..........................................................................................................................................31
3.4.6 Schematics of the user configurable FPGA (XILINX) .......................................................................................31
4The camera output timing charts................................................................................................................................. 32
4.1 The horizontal timing................................................................................................................................................ 32
4.1.1 Color Bayer order (This information is only for STC-GEC33OX)......................................................................32
4.2 The vertical timing .................................................................................................................................................... 33
4.2.1 Full scanning..................................................................................................................................................... 33
4.2.2 AOI .................................................................................................................................................................... 34
4.3 The transferring image ............................................................................................................................................. 35
