2.3 DRIVE READY (CONTROL PCB/STEPPER PCB)
The
drive ready condition occurs when the disk spindle speed
is
above
9S
o
/0
of its nominal velocity
(@
2968
RPM's).
The
ready circuit
is
derived by comparing the time between two successive index pulses to a fixed
time reference. The index detection circuit consists of
an
op amp differentiator and a one shot schmitt trig-
ger. A zero detection at the output of the differentiator circuit would generate a
10p,s
pulse at the output of
IC
7B7. The frequency of the index pulse
is
depended upon the rated rotational velocity of the disk. The fre-
quency period
is
equal to 19.2ms when the disk
is
rotating at the rated speed
(312S
rpm).
At the Stepper
PCB
an
active low index signal presets the parallel inputs to counters 1E and
2E.
These
counters are clocked by a
271
Khz
signal. It takes approximately 20 ms for 1Eand
2E
to overflow. A low, out
of counter 1
E14,
resets speed latches 1D and
SF.
The
speed latches will remain cleared if the time between
two index pulses
is
greater than 20.04 ms, indicating a not ready condition. When the disk
is
rotating above
9S
o
/0
of its nominal rotational speed, incoming indexes will preset 1E and
2E
before they time out. The next
index signal will set latch
SF
and
SF6
will go low indicating
an
active ready condition.
2.4 AUTO RECAL (STEPPER LOGIC P.C.B.)
An
Auto Recal
is
performed if two basic conditions are satisfied: One
is
that drive ready has to be
in
the ac-
tive state, and the other
is
that the heads must not be positioned over track zero. Assuming that these condi-
tions are met, the following logic functions are performed. The Index signal
is
gated through IC's
3C
and 4F.
The
Step Enable signal is
in
the inactive state, which allows the index signal to be used
as
a pseudo step
signal.
The
Auto Recal latch
(3C)
is
currently
in
the set position, indicating the direction of motion of the
read/write heads will begin to recalibrate
in
the normal mode of operation until the track zero phase (phase
A)
is
detected. The seek settle timer 1
Band
2B
will time out
in
approximately 18ms, activating Seek Com-
plete at the interface.
The
drive
is
now ready for normal operation.
2.5 STEPPING
The
STEP
interface line is a control signal, which causes the read/write heads to move
in
the direction defin-
ed
by the DIRECTION
IN
line.
The
Direction
In
line must
be
stable at least 1
OOns
before the leading edge of
the Step pulse.
There are two basic modes of operation of stepping the read/write heads, the normal mode and the buffered
mode.
In
order to implement either of these two modes of operation, there are several conditions that must
be
initiated before stepping can
be
accomplished.
1.
Write Gate must
be
inactive.
2.
Drive Select must
be
active.
3.
Ready must be active, and Seek Complete true.
2.5.1
BUFFERED MODE STEPPING
In
this mode, the step pulses are received at a high rate (pulse period separation between
3.0p,s
and
200p,s),
and buffered into step counters 4B and
SE.
Once all step pulses have been received,
s"'tep
rate timer
SA
14
will output a low, which
is
gated through IC's
3D1
0,
3ES
and
4FS.
This logic function
is
used to prevent any
more step pulses from being received.
The
actual stepping operation will now begin, depending upon the step count loaded into the step count buf-
fers, 4B and
SE.
For discussion, assume a
20
10 track seek operation.
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