Silicon Laboratories Si5341 Manuale utente

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si5341/40

LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT

CLOCK GENERATOR

Features

Applications

Description

The any-frequency, any-output Si5341/40 clock generators combine a wide-band

PLL with proprietary MultiSynth fractional synthesizer technology to offer a

versatile and high performance clock generator platform. This highly flexible

architecture is capable of synthesizing a wide range of integer and non-integer

related frequencies up to 800 MHz on 10 differential clock outputs while

delivering sub-100 fs rms phase jitter performance and 0 ppm error. Each of the

clock outputs can be assigned its own format and output voltage enabling the

Si5341/40 to replace multiple clock ICs and oscillators with a single device

making it a true “clock tree in a chip”.

The Si5341/40 can be quickly and easily configured using ClockBuilder Pro

software. Custom part numbers are automatically assigned using a

ClockBuilderPro for fast, free, and easy factory programming, or the Si5341/40

can be programmed in-circuit via I2C and SPI serial interface.

Generates free-running or

synchronous output clocks

MultiSynth™ technology enables

any-frequency synthesis on any-

output with 0 ppm frequency

accuracy with respect to the input

Highly configurable outputs

compatible with LVDS, LVPECL,

LVCMOS, HCSL, or programmable

voltage swing and common mode

Excellent jitter: <100 fs RMS typ

Input frequency range:

External crystal: 25, 48-54 MHz

Differential clock: 10 to 750 MHz

LVCMOS clock: 10 to 250 MHz

Output frequency range:

Differential: 100 Hz to 800 MHz

LVCMOS: 100 Hz to 250 MHz

Output-output skew: <100 ps

Adjustable output-output delay

Optional zero delay mode

Independent glitchless on-the-fly

output frequency changes

DCO mode with frequency

increment and decrement as low as

0.001 ppb/step

Core voltage:

VDD: 1.8 V ±5%

VDDA: 3.3 V ±5%

Independent output supply pins:

3.3V, 2.5V, or 1.8V

Built-in power supply filtering

Status monitoring: LOS, LOL

Serial Interface: I2C or SPI (3-wire

or 4-wire)

In-circuit programmable with non-

volatile OTP memory (2x

programmable)

ClockBuilder ProTM software utility

simplifies device configuration and

assigns customer part numbers

Si5341: 4 input, 10 output, 64 QFN

Si5340: 4 input, 4 output, 44 QFN

Temperature range: –40 to +85 °C

Pb-free, RoHS-6 compliant

Clock tree generation replacing

XOs, buffers, signal format

translators

Any-frequency synchronous clock

translation

Clocking for FPGAs, processors,

memory

Ethernet switches/routers

OTN framers/mappers/processors

Test equipment & instrumentation

Broadcast video

Ordering Information:

See section 7

Pin Assignments

GND

Pad

IN1

IN_SEL0

IN_SEL1

SYNC

RST

INTR

VDDA

IN2

SCLK

A0/CS

SDA/SDIO

A1/SDO

VDD

RSVD

VDDO0

OUT0

FDEC

OUT1

VDDO2

OUT2

FINC

LOL

VDD

OUT6

VDDO6

OUT5

VDDO5

I2C_SEL

OUT4

VDDO4

OUT3

VDDO3

VDDO7

OUT7

VDDO8

OUT8

OUT9

VDDO9

VDD

FB_IN

IN0

VDDO1

Si5341 64QFN

Top View

RSVD

GND

Pad

IN1

IN_SEL0

INTR

RST

VDDA

IN2

A0/CS

SDA/SDIO

A1/SDO

OUT0

VDDO0

SCLK

I2C_SEL

OUT1

VDDO1

VDDO3

OUT3

FB_IN

IN0

Si5340 44QFN

Top View

VDD

OUT2

VDDO2

VDDS

LOL

LOS_XAXB

VDD

IN_SEL1

IN2 11 23

NC 22

VDD

Si5341/40

2 Preliminary Rev. 0.9

Functional Block Diagram

Si5341/40

FB_IN

IN0

IN_SEL

IN1

IN2

XTAL

÷INT

OSC

Multi

Synth OUT0

÷INT

OUT1

÷INT

OUT2

÷INT

OUT3

÷INT

OUT4

÷INT

OUT5

÷INT

OUT6

÷INT

OUT7

÷INT

OUT8

÷INT

OUT9

÷INT

Multi

Synth

Multi

Synth

Multi

Synth

Multi

Synth

Si5340 Si5341

PLL

÷INT

NVM

I2C/SPI

Control/

Status

Si5341/40

Preliminary Rev. 0.9 3

TABLE OFCONTENTS

1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.1. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.2. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.3. Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.4. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.5. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.6. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.7. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.8. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.9. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

8. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

8.1. Si5341 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

8.2. Si5340 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

11. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Appendix—Advance Product Information Revision History . . . . . . . . . . . . . . . . . . . . . . .46

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Si5341/40

4 Preliminary Rev. 0.9

1. Typical Application Schematic

Figure 1. Using The Si5341 to Replace a Discrete Clock Tree

PCB Clock Tree

Level

Translator

Clock

Generator

161.1328125

MHz

Buffer

133.33 MHz

Buffer

One Si5341 replaces:

3x crystal oscillators (XO)

4x buffers

1x clock generator

2x level translators

1x delay line

“Clock Tree

On-a-Chip”

25 MHz 4x 200 MHz

2.5V LVCMOS

2x 161.1328125 MHz

LVDS 2x 133.33 MHz

1.8V LVCMOS

Buffer

125 MHz

Level

Translator

Buffer

Delay Line

4x 125 MHz

3.3V LVCMOS

3x 125 MHz

LVPECL

Si5341 Nn0

Nd0

LPF

PLL

÷Mn

Free Run

Mode

OSC

Nn1

Nd1

N2n

N2d

N3n

N3d

N4n

N4d

161.1328125MHz

133.33MHz

125MHz

200MHz

1x 161.1328125 MHz

LVDS

1x 161.1328125 MHz

LVDS

2x 133.33 MHz

1.8V LVCMOS

2x 125 MHz

3.3V LVCMOS

2x 125 MHz

3.3V LVCMOS

2x 200 MHz

2.5V LVCMOS

2x 200 MHz

2.5V LVCMOS

1x 125 MHz

LVPECL

1x 125 MHz

LVPECL

1x 125 MHz

LVPECL

25 MHz

Si5341/40

Preliminary Rev. 0.9 5

2. Electrical Specifications

Table 1. Recommended Operating Conditions

(VDD =1.8V±5%,V

DDA =3.3V±5%,T

A= –40 to 85 °C)

Parameter Symbol Min Typ Max Units

Ambient Temperature TA–402585°C

Junction Temperature TJMAX ——125°C

Core Supply Voltage VDD 1.71 1.80 1.89 V

VDDA 3.14 3.30 3.47 V

Output Driver Supply Voltage VDDO 3.14 3.30 3.47 V

2.38 2.50 2.62 V

1.71 1.80 1.89 V

*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 2. DC Characteristics

(VDD =1.8V±5%,V

DDA =3.3V±5%,V

DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Core Supply Current IDD Si5341 or

Si5340 Notes 1,2—98140mA

IDDA —115125mA

Output Buffer Supply Current IDDOx LVPECL Output3

@ 156.25 MHz —2325mA

LVDS Output3

@ 156.25 MHz —1618mA

3.3V LVCMOS4output

@ 156.25 MHz —1926mA

2.5 V LVCMOS4output

@ 156.25 MHz —1519mA

1.8 V LVCMOS4output

@ 156.25 MHz —1113mA

Total Power Dissipation PdSi5341 Notes 1,5— 836 945 mW

Si5340 Notes 2,5— 645 — mW

Notes:

1. Si5341 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.

2. Si5340 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.

3. Differential outputs terminated into an AC coupled 100 load.

4. LVCMOS outputs measured into a 6 inch 50 PCB trace with 5 pF load.

5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board

(EVB) is not available. All EVBs support detailed current measurements for any configuration.

100

OUT

IDDO

Differential Output Test Configuration

OUTa

IDDO

5 pF

LVCMOS Output Test Configuration

6 inch

OUTb

Si5341/40

6 Preliminary Rev. 0.9

Table 3. Input Specifications

(VDD =1.8V±5%,V

DDA =3.3V±5%,T

A=–40to85°C)

Parameter Symbol Test Condition Min Typ Max Units

Differential or Single-Ended - AC Coupled (IN0/IN0, IN1/IN1, IN2/IN2, FB_IN/FB_IN)

Input Frequency Range fIN_DIFF 10 — 750 MHz

Voltage Swing VIN fin < 400 MHz 100 — 1000 mVpp_se

600 MHz < fin <

800 MHz 225 — 1000 mVpp_se

fin > 800 MHz 375 — 1000 mVpp_se

Slew Rate1, 2 SR 400 — — V/µs

Duty Cycle DC 40 — 60 %

Capacitance CIN —2 — pF

LVCMOS - DC Coupled (IN0, IN1, IN2)

Input Frequency fIN_CMOS 10 — 250 MHz

Input Voltage VIL -0.1 — 0.33 V

VIH 0.80 — — V

Slew Rate1, 2 SR 400 — — V/µs

Duty Cycle DC Clock Input 40 — 60 %

Minimum Pulse Width PW Pulse Input 1.6 — — ns

Input Resistance RIN —8 — kΩ

REFCLK (Applied to XA/XB)

REFCLK Frequency fIN_REF Frequencyrange

for best output

jitter performance

48 — 54 MHz

10 — 120 MHz

Input Voltage Swing VIN 350 — 1600 mVpp_se

Slew rate1, 2 SR Imposed for best

jitter performance 400 — — V/µs

Input Duty Cycle DC 40 — 60 %

Notes:

1. Imposed for jitter performance.

2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) * VIN_Vpp_se) / SR.

3. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD.

Si5341/40

Preliminary Rev. 0.9 7

Table 4. Control Input Pin Specifications

(VDD =1.8V±5%,V

DDA =3.3V±5%,V

DDS = 3.3 V ±5%, 1.8 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Si5341 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST, OE, SYNC, A1, SCLK, A0/CS, FINC, FDEC)

Input Voltage VIL -0.1 — 0.3xVDDIO*V

VIH 0.7xVDDIO1—3.6 V

Input Capacitance CIN —2— pF

Input Resistance IL—20— k

Minimum Pulse Width PW RST 50 — — ns

Si5340 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST, OE, A1, SDA, SDI, SCLK, A0/CS)

Input Voltage VIL –0.1 — 0.3xVDDIO*V

VIH 0.7xVDDIO*—3.6 V

Input Capacitance CIN —2— pF

Input Resistance IL—20— k

Minimum Pulse Width PW RST 50 — — ns

*Note: VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD.

Table 5. Differential Clock Output Specifications

(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Output Frequency fOUT 0.0001 — 800 MHz

Duty Cycle DC f < 400 MHz 48 — 52 %

400 MHz < f < 800 MHz 45 — 55 %

Output-Output Skew TSK Differential Output — — 100 ps

OUT-OUT Skew TSK_OUT Measured from the positive

to negative output pins ——100 ps

Notes:

1. Normal swing mode, high swing mode, Vswing and Cmode settings are programmable through register settings and

can be stored in NVM. Each output driver can be programmed independently.

2. Not all combinations of voltage swing and common mode voltages settings are possible.

3. Common mode voltage min/max variation = ±4% from typical value

4. Driver output impedance depends on selected output mode (Normal, High).

5. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/

3.3 V = 100 mVpp) and noise spur amplitude measured.

OUTx

OUTx Vpp_se

Vpp_se Vpp_diff = 2*Vpp_se

Vcm

Vcm Vcm

Si5341/40

8 Preliminary Rev. 0.9

Output Voltage Swing1Normal Swing Mode

VOUT VDDO =3.3V,

2.5 V, or 1.8 V LVDS 370 470 570 mVpp_se

LVPECL 650 820 1050

High Swing Mode

VOUT VDDO =3.3V,

2.5 V, or 1.8 V LVDS 310 420 530 mVpp_se

VDDO =3.3V

or 2.5 V LVPECL 590 830 1060

Common Mode Voltage1, 2, 3 Normal Swing or High Swing Modes

VCM VDDO = 3.3 V LVDS 1.12 1.23 1.34 V

LVPECL 1.90 2.0 2.13

VDDO = 2.5 V LVPECL

LVDS 1.17 1.23 1.3

Rise and Fall Times

(20% to 80%) tR/tFNormal Swing Mode — 170 220 ps

High Swing Mode — 250 320

Differential Output Impedance4ZONormal Swing Mode — 100 — 

High Swing Mode — Hi-Z — 

Table 5. Differential Clock Output Specifications (Continued)

(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Notes:

1. Normal swing mode, high swing mode, Vswing and Cmode settings are programmable through register settings and

can be stored in NVM. Each output driver can be programmed independently.

2. Not all combinations of voltage swing and common mode voltages settings are possible.

3. Common mode voltage min/max variation = ±4% from typical value

4. Driver output impedance depends on selected output mode (Normal, High).

5. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/

3.3 V = 100 mVpp) and noise spur amplitude measured.

OUTx

OUTx Vpp_se

Vpp_se Vpp_diff = 2*Vpp_se

Vcm

Vcm Vcm

Si5341/40

Preliminary Rev. 0.9 9

Power Supply Noise Rejection5PSRR Normal Swing Mode

10 kHz sinusoidal noise — –93 — dBc

100 kHz sinusoidal noise — –93 —

500 kHz sinusoidal noise — –84 —

1 MHz sinusoidal noise — –79 —

High Swing Mode

10 kHz sinusoidal noise — –98 — dBc

100 kHz sinusoidal noise — –95 —

500 kHz sinusoidal noise — –84 —

1 MHz sinusoidal noise — –76 —

Output-output Crosstalk XTALK Measured spur from adja-

cent output —–73— dBc

Table 6. Output Status Pin Specifications

(VDD =1.8V±5%,V

DDA =3.3V±5%,V

DDS = 3.3 V ±5%, 1.8 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Si5341 Status Output Pins (LOL, INTR)

Output Voltage VOH IOH = –2 mA VDDIO*x 0.75 — — V

VOL IOL = 2 mA — — VDDIO1x 0.15 V

Si5340 Status Output Pins (INTR)

Output Voltage VOH IOH = –2 mA VDDIO*x 0.75 — — V

VOL IOL = 2 mA — — VDDIO1x 0.15 V

Si5340 Status Output Pins (LOL, LOS_XAXB)

Output Voltage VOH IOH = –2 mA VDDS x 0.85 — — V

VOL IOL = 2 mA — — VDDS x 0.15 V

*Note: VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD.

Table 5. Differential Clock Output Specifications (Continued)

(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Notes:

1. Normal swing mode, high swing mode, Vswing and Cmode settings are programmable through register settings and

can be stored in NVM. Each output driver can be programmed independently.

2. Not all combinations of voltage swing and common mode voltages settings are possible.

3. Common mode voltage min/max variation = ±4% from typical value

4. Driver output impedance depends on selected output mode (Normal, High).

5. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/

3.3 V = 100 mVpp) and noise spur amplitude measured.

OUTx

OUTx Vpp_se

Vpp_se Vpp_diff = 2*Vpp_se

Vcm

Vcm Vcm

Si5341/40

10 Preliminary Rev. 0.9

Table 7. LVCMOS Clock Output Specifications

(VDD = 1.8 V ±5%, VDDA =3.3V±5%,V

DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Output Frequency 0.0001 — 250 MHz

Duty Cycle DC f < 400 MHz 47 — 53 %

400MHz<f<800MHz 45 — 55

Output-to-Output Skew TSK ——100ps

Output Voltage High1, 2, 3 VOH VDDO = 3.3 V

CMOS1 IOH = –10 mA VDDO x 0.85 — — V

CMOS2 IOH = –12 mA — —

CMOS3 IOH = –17 mA — —

VDDO = 2.5 V

CMOS1 IOH = –6 mA VDDO x 0.85 — — V

CMOS2 IOH = –8 mA — —

CMOS3 IOH = –11 mA — —

VDDO = 1.8 V

CMOS1 IOH = –3 mA VDDO x 0.85 — — V

CMOS2 IOH = –4 mA — —

CMOS3 IOH = –5 mA — —

Notes:

1. Driver strength is a register programmable setting and stored in NVM. Options are CMOS1, CMOS2, CMOS3.

2. IOL/IOH is measured at VOL/VOH as shown in the DC test configuration

3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 Ohm PCB trace. A 5 pF

capacitive load is assumed.

DC Test Configuration

IOL/IOH

VOL/VOH

5 pF

AC Test Configuration

Zs + Rs = 50 Ohms

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