3.9
Dynamic
Memory
Refresh.
TheCPU
incorporates
built-in
dynamic
RAM
refreshcircuitry.AspartoftheinstructionOPcodefetchcycle,
theCPU
performs
a
memory
requestafter
first
placing
the
refresh
addressonthelowereightbitsoftheaddressbus.Attheendofthe
cycletheaddressisincrementedsothatover255fetchcycles,each
rowofthedynamicRAMisrefreshed.Thismechanismonlyappliesto
theoptional32kexpansionRAMinthe48kSpectrum.Analternative
refreshmethodisadaptedforthestandard16KRAM.
4.MEMORYORGANISATION
4.1Inthe
standard
16k
Spectrum
there
are32k
bytes
of
addressable
memory
equallydividedbetweenROMandRAM.
4.2The
lower
16k
bytes
of
memory
(addresses
0000
-
3FFF)
are
implemented
ina singleROM(IC5)whichholdsthemonitorprogram.Thisprogram
isa complexZ80machinecodeprogramdividedbroadlyintothreeparts
one
eachcovering
the
input/outputroutines,
the
BASIC
interpreter
and
expressionhandling.Detailsoftheprogramcontent,althoughoutside
the
scope
of
this
manual,
are
referred
toas
necessary.
4.3The
upper
16
bytes
of
memory
(addresses
4000
-
7FFF)
are
implemented
using
eight
16kbit
dynamic
RAMs
(IC6-IC13).
Approximatelyhalf
of
this
space
is
available
tothe
user
for
writing
BASIC
or
machine
code
programs.Theremainderisusedtoholdthesystemvariables
including6kbytesreservedforthememorymappeddisplayarea.
4.4Inthe48kSpectrumanadditional32kbytesofRAMareprovided
(addresses
8000
-
FFFF)
which
are
implementedusing
eight
32kbit
dynamic
RAMs
(IC15-IC32).
The
RAM,providing
extra
memory
space
for
theuser,isnormallyfittedduringmanufacturebutmaybeadded
retrospectively
using
the
RAM
expander
kit.
In
addition
tothe
RAMs,
thekitincludestheaddressmultiplexerandread/writecontrolICs
IC23-IC26.
Board
space
andthe
necessary
discrete
components
are
alreadyprovidedontheboard.
4.5Read/WriteOperations
4.5.1Thefollowingdescriptionshouldbereadinconjunctionwiththe
circuitdiagramsgiveninFigures1.4and1.5.
4.5.2ReadOnlyMemory(ICS).TheCPUaddressestheROMdirectlyduring
memoryreadcyclesusingtheaddressbusA13-AO.MREQandRDenable
theROMandtheROMoutputsrespectively.A thirdinput(CS)derived
bytheULA'ROMCS)selectstheROM,providedthehigherorderaddress
bitsA14andA15arebothlow.Thesearereservedforaccessingthe
RAMmemorywhichstartswithaddress4000(i.e.addressA14set).An
externalROM1Cselectinput,suppliedviatheexpansionportonpin
25A,selectivelydisablestheon-boardROMbypullingtheselectinput
high.ByvirtueofR33placedontheULAsideoftheROMtheULA
ROMCSoutputiseffectivelyinhibited.Interface1 usesthis
1.4
