Singmai Electronics PT9 Manuale utente

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PT9 User Manual Revision 0.3Page 1 of 38

PT9

Multi-standard

Video Encoder

with cross-colour reduction

User Manual

Revision 0.3

9th June 2018

SingMai Electronics

PT9 User Manual Revision 0.3Page 2 of 38

Revisions

Date

Revisions

Version

19-11-2015

First draft.

0.1

29-08-2017

Revisions to comb filter.

Cross-colour reduction description added.

Pre-emphasis added.

Cross luma reduction removed.

Additions to technical description.

0.2

09-06-2018

Minor correction to Table 8.

0.3

SingMai Electronics

PT9 User Manual Revision 0.3Page 3 of 38

Contents

Revisions .................................................................................................................................................. 2

Contents...................................................................................................................................................3

Tables .......................................................................................................................................................3

Figures...................................................................................................................................................... 3

1. Introduction ...................................................................................................................................5

2. PT9 Module description.................................................................................................................6

3. Signal Interconnections.................................................................................................................7

4. Signal Levels...................................................................................................................................9

5. Test signals................................................................................................................................... 10

6. Technical Overview....................................................................................................................... 11

PT9_encoder.v................................................................................................................................... 11

PT9_Register_control.v..................................................................................................................... 11

PT9_BT656_receiver.v....................................................................................................................... 11

PT9_SPG.v .......................................................................................................................................... 11

PT9_Subcarrier_gen.v .......................................................................................................................12

PT9_Chroma_modulator.v................................................................................................................12

PT9_ROM.v ........................................................................................................................................12

PT9_output_proc.v............................................................................................................................12

PT9_Comb_filter.v............................................................................................................................ 14

ram_infer_generic.v ......................................................................................................................... 14

7. Cross-colour reduction .................................................................................................................15

8. Register interface ........................................................................................................................ 19

9. Register descriptions ...................................................................................................................20

10. Horizontal timing registers ...................................................................................................... 23

11. Default Register Settings............................................................................................................. 25

12. Interfacing to a DAC..................................................................................................................... 27

13. Specification .............................................................................................................................28

14. Measurements..........................................................................................................................29

Tables

Table 1 PT9 Altera FPGA resource requirements ...................................................................................5

Table 2 PT9 module heirachy. .................................................................................................................6

Table 3 Input/Output signals...................................................................................................................7

Table 4 BT656 Signal Levels....................................................................................................................9

Table 5 BT656 test waveform (525 line)............................................................................................... 10

Table 6 BT656 test waveform (625 line) .............................................................................................. 10

Table 7 Register descriptions................................................................................................................ 22

Table 8 Default Register settings .........................................................................................................26

Table 9 PT9 Specifications. ...................................................................................................................28

Figures

Figure 1 PT9 Interconnection diagram. ..................................................................................................7

Figure 2 CVBS output levels ...................................................................................................................9

Figure 3 PT9 Block Diagram. .................................................................................................................. 11

Figure 4 Chroma modulation filter. .......................................................................................................12

Figure 5 Luma interpolation filter frequency response........................................................................13

Figure 6 Sinx/x filter frequency response. ............................................................................................13

Figure 7 NTSC Pre-emphasis filter......................................................................................................... 14

Figure 8 PAL pre-emphasis filter........................................................................................................... 14

SingMai Electronics

PT9 User Manual Revision 0.3Page 4 of 38

Figure 9 PAL frequency spectrum .........................................................................................................15

Figure 10 Zone plate image after line comb decoding. ....................................................................... 16

Figure 11 Zone plate image after frame comb decoding. .....................................................................17

Figure 12 Zone plate image, line comb decoded from PT9 encoder................................................... 18

Figure 13 NTSC zone plate with line comb decoder. Left: conventional encoder/line comb decoder.

Right: PT9 encoder with conventional line comb decoder. ................................................................ 18

Figure 14 Control interface Timing........................................................................................................ 19

Figure 15 NTSC horizontal timing.......................................................................................................... 23

Figure 16 PAL-BG horizontal timing ......................................................................................................24

Figure 17 Interfacing to a DAC............................................................................................................... 27

Figure 18 NTSC Vertical blanking interval .............................................................................................29

Figure 19 NTSC Horizontal Timing.........................................................................................................30

Figure 20 NTSC 75% Colour bar..............................................................................................................30

Figure 21 NTSC Chroma/Luma delay ......................................................................................................31

Figure 22 NTSC K Factor .........................................................................................................................31

Figure 23 NTSC Multiburst (No sinx/x correction) ............................................................................... 32

Figure 24 NTSC Noise Spectrum (Black)............................................................................................... 32

Figure 25 NTSC Noise Spectrum (luma ramp)......................................................................................33

Figure 26 PAL Vertical blanking interval...............................................................................................33

Figure 27 PAL Horizontal timing ...........................................................................................................34

Figure 28 PAL 75% Colour bars ..............................................................................................................34

Figure 29 PAL Chroma/Luma delay.......................................................................................................35

Figure 30 PAL K-factor........................................................................................................................... 35

Figure 31 PAL Multiburst (no sinx/x correction)...................................................................................36

Figure 32 PAL Noise spectrum (black).................................................................................................. 37

Figure 33 PAL Luma non-linearity .........................................................................................................38

SingMai Electronics

PT9 User Manual Revision 0.3Page 5 of 38

1. Introduction

PT9 is a broadcast quality, multi-standard, video encoder supporting PAL-M/N/B/D/G/H/I and NTSC-

M/J outputs.

The intellectual property block accepts BT656 formatted data, in either 8 or 10 bit format, with the

associated 27MHz clock, and it encodes this data to a 10 bit, digital composite video output at

27MHz, which can be used to directly drive a digital to analogue converter, modulator or other

output device.

PT9 includes special cross-colour reduction circuitry, particularly of help in reducing artifacts when

used with a line comb video decoder.

The encoder can also be set to a free-run mode in which it ignores the BT656 timing information

and data and uses the clock input to generate a black and burst output.

Control and status registers are written to and read from using a conventional 8 bit wide

microprocessor interface.

The Altera FPGA usage (taken from the SM05 evaluation board compilation statistics) is shown in

Table 1.

Logic Elements

Memory Bits

M9K blocks

9x9 Multipliers

18x18 multipliers

9323

218112

Table 1 PT9 Altera FPGA resource requirements

The ASIC equivalent gate count is approximately 112k gates. The memory constitutes:

1 512 x 24 = 12288 bit single port ROM

4 2048 x 11 bit single port RAM = 90112 bits.

2 2048 x 10 bit single port RAM = 40960 bits.

2 2048 x 9 bit single port RAM = 36864 bits.

2 2048 x 12 bit single port RAM = 49152 bits.

SingMai Electronics

PT9 User Manual Revision 0.3Page 6 of 38

2. PT9 Module description

The PT9 encoder comprises 10 Verilog modules. PT9_encoder.v is the top level module of the

hierarchy; six of the other modules are instantiated from it.

Top level

2nd level

3rd level

4th level

PT9_encoder.v

PT9_Register_control.v

PT9_BT656_receiver.v

PT9_SPG.v

PT9_Subcarrier_gen.v

PT9_ROM.v

PT9_Chroma_modulator.v

PT9_output_proc.v

PT9_Comb_filter.v

ram_infer_generic.v

Table 2 PT9 module heirachy.

SingMai Electronics

PT9 User Manual Revision 0.3Page 7 of 38

3. Signal Interconnections

The PT9 signal interconnect diagram is shown in Figure 1.

Figure 1 PT9 Interconnection diagram.

The signal descriptions are shown in Table 3, below.

Signal

Description

Clock

27MHz clock input synchronous with the BT656 input data. The BT656

data should be stable at the rising edge of this clock.

Clock2x

54MHz clock input (2x Clock). The rising edge of this input should be

synchronous with the rising edge of Clock. This clock is used for the

single port RAM.

BT656_data[9..0]

BT656 compliant input data, sampled on the rising edge of Clock. If the

input is 8-bit the bottom 2 bits should be connected to ground (logic

‘0’).

RESETn

Asynchronous active low reset signal. Asserting this input sets all the

control registers to their default value and resets all registers.

A[5:0]

Control address bus input used to select the control register to be

written to/read from.

Din[7:0]

Control data input bus.

PT9_CSn

Control chip select input, active low. Used in combination with the WRn

input to control writing to the control registers.

PT9_WRn

Active low write enable input. Used in combination with the CSn input

to control writing to the control registers.

PT9_Register_out[7:0]

Control output data bus. Outputs the control/status register data

selected by the A[5:0] bus.

CVBS_out[9..0]

The digital composite output. The output format is straight binary with

bit 9 being the MSB. The output is valid on the rising edge of the Clock

input.

Comp_Sync

Composite sync signal output.

Table 3 Input/Output signals

SingMai Electronics

PT9 User Manual Revision 0.3Page 8 of 38

The Verilog instantiation of PT9 is shown below:

// Instantiate Video encoder (PT9_encoder)

PT9_encoder PT9_encoder_inst

(

.Clock(Clock_sig) , // input Clock_sig

.Clock2x(Clock2x_sig) , // input Clock2x_sig

.BT656_data(BT656_data_sig) , // input [9:0] BT656_data_sig

.RESETn(RESETn_sig) , // input RESETn_sig

.A(A_sig) , // input [5:0] A_sig

.Din(Din_sig) , // input [7:0] Din_sig

.PT9_CSn(PT9_CSn_sig) , // input PT9_CSn_sig

.PT9_WRn(PT9_WRn_sig) , // input PT9_WRn_sig

.PT9_Register_out(PT9_Register_out_sig) , // output [7:0] PT9_Register_out_sig

.CVBS_out(CVBS_out_sig) , // output [9:0] CVBS_out_sig

.Comp_Sync(Comp_Sync_sig) // output Comp_Sync_sig

);

SingMai Electronics

PT9 User Manual Revision 0.3Page 9 of 38

4. Signal Levels

The expected signal levels for the BT656 input are shown in Table 4, below.

10-bit YCbCr signal Levels 100/0/100/0

White

940

512

Yellow

840

585

Cyan

678

663

Green

578

215

137

Magenta

426

809

887

Red

326

361

960

Blue

164

960

439

Black

512

10-bit YCbCr signal Levels 75/0/75/0

White

940

512

Grey

721

512

Yellow

646

176

567

Cyan

525

625

176

Green

450

289

231

Magenta

335

735

793

Red

260

399

848

Blue

139

848

457

Black

512

Table 4 BT656 Signal Levels

The resulting nominal output levels for a 100% PAL colour bar input are shown in Figure 2.

Figure 2 CVBS output levels

SingMai Electronics

PT9 User Manual Revision 0.3Page 10 of 38

5. Test signals

The PT9 is supplied with BT656 test waveforms to facilitate testing and verification.

The waveforms are supplied as Excel spreadsheets and are 75% saturation colour bars. Other

waveforms can be supplied on request for a small charge.

There are four elements to the complete frame of video and each element consists of 1716 (515

line) or 1728 (625 line) samples in a multiplexed Cb,Y,Cr,Y sequence. Each sample of each element

should be clocked at 27MHz.

For 525 line standards the elements should be selected according to the following table:

Line No.s

Pattern

Element

4-19, 264, 265

F0V1

1-3, 266-282

F1V1

20-263

75% Bars F0

283-525

75% Bars F1

Table 5 BT656 test waveform (525 line)

For 625 line standards the elements should be selected according to Table 6.

Line No.s

Pattern

Element

1-22, 311, 312

Fsync F1

313-335, 624, 625

Fsync F2

23-310

75% Bars F1

336-623

75% Bars F2

Table 6 BT656 test waveform (625 line)

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