Skyworks Si5386 Manuale utente

Si5386 Rev. E Reference Manual

Overview

This reference manual is intended to provide system, PCB design, signal integrity, and

software engineers the necessary technical information to successfully use the Si5386

device in end applications. The official device specifications can be found in the Si5386

data sheet.

The Si5386 is a high-performance, clock generator for small cell applications that de-

mand the highest level of integration and phase noise performance. Based on Skyworks

Solutions’ fourth-generation DSPLL technology, the Si5386 combines frequency synthe-

sis and jitter attenuation in a highly integrated digital solution. A single low phase noise

XO connected to the XA/XB input pins provides the reference for the device. This all-dig-

ital solution provides superior performance that is highly immune to external board distur-

bances such as power supply noise.The device configuration is in-circuit programmable

via an SPI or I2C serial interface and is easily stored in non-volatile memory (NVM) for

applications which require preconfigured clocks at start-up or after reset.

Work Flow Expectations with ClockBuilder™ Pro and the Register Map

This reference manual is to be used to describe all the functions and features of the

parts in the product family with register map details on how to implement them. It is im-

portant to understand that the intent is for customers to use the ClockBuilder™ Pro soft-

ware to provide the initial configuration for the device. Although the register map is docu-

mented, all the details of the algorithms to implement a valid and optimum frequency

plan are fairly complex and are beyond the scope of this document. Real-time changes

to the frequency plan and other operating settings are supported by the devices. Pro-

gramming the Si5386 is made easy with Skyworks' ClockBuilder Pro software available

at https://www.skyworksinc.com/en/Application-Pages/Clockbuilder-Pro-Software.

RELATED DOCUMENTS

•Si5386 Data Sheet

•Si5386A-E-EVB Evaluation Kit

•Si5386A-E-EVB User Guide

•Si5386A-E-EVB Schematic, BOM and

layout files

•Recommended XO Reference Manual

•AN1165: Configuring Si538x Devices for

JESD204B/C Wireless Applications

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Table of Contents

1. Functional Description............................5

1.1 DSPLL.................................5

1.2 LTE Frequency Configuration .........................5

1.3 Configuration for JESD204B Subclass 1 Clock Generation ...............7

1.4 DSPLL Loop Bandwidth ...........................8

1.4.1 Fastlock ...............................8

1.4.2 Holdover Exit Bandwidth .........................9

1.5 Dividers Overview .............................9

2. Modes of Operation ............................ 10

2.1 Reset and Initialization ...........................11

2.1.1 Updating Registers During Device Operation ..................12

2.1.2 NVM Programming ...........................13

2.2 Free Run Mode ..............................13

2.3 Lock Acquisition Mode ...........................13

2.4 Locked Mode ..............................13

2.5 Holdover Mode ..............................14

2.6 VCO Freeze Mode.............................16

3. Clock Inputs............................... 17

3.1 Input Source Selection ...........................17

3.1.1 Manual Input Switching..........................17

3.1.2 Automatic Input Switching .........................18

3.2 Types of Inputs ..............................19

3.2.1 Unused Inputs.............................21

3.2.2 Use Case Scenario: Using More Than Two Inputs.................22

3.2.3 Hitless Input Switching with Phase Buildout ...................22

3.2.4 Ramped Input Switching .........................23

3.2.5 Hitless Switching, Loss of Lock (LOL), and Fastlock ................23

3.2.6 Glitchless Input Switching .........................23

3.2.7 Slew Rate Considerations .........................24

3.3 Fault Monitoring .............................25

3.3.1 Input Loss of Signal (LOS) Fault Detection ...................26

3.3.2 Out-of-Frequency (OOF) Detection......................28

3.3.3 Loss of Lock (LOL) Fault Monitoring .....................30

3.3.4 Interrupt Pin (INTR) ...........................32

4. Output Clocks .............................. 34

4.1 Output Crosspoint Switch ..........................34

4.1.1 Output R Divider Synchronization ......................35

4.2 Performance Guidelines for Outputs .......................36

4.2.1 Optimizing Output Phase Noise .......................37

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4.3 Output Signal Format ............................37

4.4 Output Driver Supply Select .........................38

4.5 Differential Outputs ............................39

4.5.1 Differential Output Terminations .......................39

4.5.2 Differential Output Amplitude Controls.....................40

4.5.3 Differential Output Common Mode Voltage Selection................41

4.5.4 Recommended Settings for Differential LVPECL, LVDS, HCSL, and CML .........42

4.6 LVCMOS Outputs .............................43

4.6.1 LVCMOS Output Terminations .......................43

4.6.2 LVCMOS Output Impedance and Drive Strength Selection ..............44

4.6.3 LVCMOS Output Signal Swing .......................44

4.6.4 LVCMOS Output Polarity .........................45

4.7 Output Enable/Disable ...........................46

4.7.1 Output Driver State When Disabled .....................47

4.7.2 Synchronous Output Enable/Disable Feature ..................48

4.7.3 Automatic Output Disable During LOL.....................48

4.7.4 Automatic Output Disable During LOSXAXB ..................49

4.7.5 Output Driver Disable Source Summary ....................50

4.8 Static Output Skew Control ..........................51

4.9 Dynamic Output Skew Control .........................53

5. Zero Delay Mode ............................. 54

6. Serial Interface.............................. 56

6.1 I2C Interface ...............................58

6.2 SPI Interface...............................60

7. Field Programming ............................ 65

8. XAXB External References ......................... 66

8.1 Performance of External References ......................66

9. XO and Device Circuit Layout Recommendations................. 67

9.1 Si5386 64-Pin QFN External XO Layout Recommendations ...............67

10. Power Management ........................... 73

10.1 Power Management Features ........................73

10.2 Power Supply Recommendations .......................73

10.3 Power Supply Sequencing .........................74

10.4 Grounding Vias .............................74

11. Base vs. Factory Preprogrammed Devices ................... 75

11.1 "Base" Devices (a.k.a. "Blank" Devices) .....................75

11.2 "Factory Preprogrammed" (Custom OPN) Devices .................75

11.3 Part Numbering Summary ..........................75

12. Register Map .............................. 76

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12.1 Page 0 Registers.............................76

12.2 Page 1 Registers.............................91

12.3 Page 2 Registers.............................98

12.4 Page 3 Registers............................104

12.5 Page 4 Registers............................106

12.6 Page 5 Registers............................107

12.7 Page 9 Registers............................117

12.8 Page A Registers ...........................119

12.9 Page B Registers ...........................124

12.10 Page C Registers ...........................129

13. Appendix—Custom Differential Amplitude Controls ...............130

14. Revision History.............................132

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1. Functional Description

1.1 DSPLL

The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock

frequency or free run from the reference clock. It consists of a phase detector, a programmable digital loop filter, a high-performance

ultra-low-phase-noise analog VCO, and a user configurable feedback divider. Use of an external XO provides the DSPLL with a stable

low-noise clock source for frequency synthesis and for maintaining frequency accuracy in the free run or Holdover modes. No other

external components are required for oscillation. A key feature of DSPLL is providing immunity to external noise coupling from power

supplies and other uncontrolled noise sources that normally exist on printed circuit boards.

The frequency configuration of the DSPLL is programmable through the SPI or I2C serial interface and can also be stored in non-vola-

tile memory (NVM) or RAM. The combination of input dividers (P0-P3), frequency multiplication (M), output division (N), and output

division (R0A-R9A) allows the generation of a wide range of frequencies on any of the outputs. All divider values for a specific

frequency plan are easily determined using the ClockBuilder Pro software.

1.2 LTE Frequency Configuration

The device’s frequency configuration is fully programmable through the serial interface and can also be stored in non-volatile memory.

The flexible combination of dividers and a high frequency VCO allows the device to generate multiple output clock frequencies for

applications that require ultra-low phase-noise and spurious performance. The table below shows a partial list of possible output

frequencies for LTE applications. The Si5386's DSPLL core can generate up to five asynchronous frequencies. These frequencies are

distributed to the output dividers using a configurable crosspoint mux. The output R dividers allow further division for up to 12 unique

integer-related frequencies on the Si5386. The ClockBuilder Pro software utility provides a simple means of automatically calculating

the optimum divider values (P, M, N and R) for the frequencies listed below. In addition to the LTE frequencies, the Si5386 device can

simultaneously generate wireline clocks like 156.25 MHz, 155.52 MHz, 125 MHz, etc. and system clocks like 100 MHz, 33 MHz, 25

MHz, etc.

Si5386 Rev. E Reference Manual • Functional Description

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Table 1.1. Example List of Possible LTE Clock Frequencies

LTE Device Clock Fout (MHz)1

15.36

19.20

30.72

38.40

61.44

76.80

122.88

153.60

184.32

245.76

307.20

368.64

491.52

614.40

737.28

983.04

1228.80

1474.56

1638.4

1843.2

2106.51428571

2457.6

2949.12

Note:

1. R output dividers allow other frequencies to be generated. These

are useful for applications like JESD204B SYSREF clocks.

Si5386 Rev. E Reference Manual • Functional Description

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1.3 Configuration for JESD204B Subclass 1 Clock Generation

The Si5386 can be used as a high-performance, fully-integrated JEDEC JESD204B jitter cleaner while eliminating the need for discrete

VCXO and loop filter components. The Si5386 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks

(DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF

clocks to drive JESD204B ADCs, DACs, FPGAs, or other logic devices. The Si5386 will clock up to six JESD204B subclass 1 targets,

using six DCLK/SYSREF pairs. If SYSREF clocking is implemented in external logic, then the Si5386 can clock up to 12 JESD204B

targets. Not limited to JESD204B applications, each of the 12 outputs is individually configurable as a high performance output for

traditional clocking applications.

For applications which require adjustable static delay between the DCLK and SYSREF signals, the Si5386 supports up to four DCLK/

SYSREF pairs, each with independently adjustable delay. An example of an adjustable delay JESD204B frequency configuration is

shown in the following figure. In this case, the N0 divider determines the device clock frequencies while the N1-N4 dividers generate the

divided SYSREF used as the lower frequency frame clock. Each output N divider also includes a configurable delay (Δt) for controlling

deterministic latency. This example shows a configuration where all the device clocks are controlled by a single delay (Δt0) while the

SYSREF clocks each have their own independent delay (Δt1 –Δt4), though other combinations are also possible. The bidirectional

delay is programmable over ±8.6 ns in 68 ps steps. See 4.8 Static Output Skew Control for more information on delay control. The

SYSREF clock is always periodic and can be controlled (on/off) without glitches by enabling or disabling its output through register

writes.

IN_SEL[1:0]

IN0

IN0b

IN1

IN1b

IN2

IN2b

IN3/FB_IN

IN3b/FB_INb

÷P1

÷P0

÷P2

÷P3

DSPLL

LPFPD

÷M

÷N1

÷N2

÷N3

÷N4

OUT6b

VDDO6

OUT6

VDDO7

VDDO0

OUT0Ab

OUT0A

OUT0b

OUT0

÷R6

÷R0A

OUT7b

OUT7

÷R7

OUT5b

VDDO5

OUT5

÷R5

OUT1b

VDDO1

OUT1

VDDO2

÷R1

OUT2b

OUT2

÷R2

OUT8b

VDDO8

OUT8

÷R8

OUT3b

VDDO3

OUT3

VDDO4

÷R3

OUT4b

OUT4

÷R4

VDDO9

OUT9b

OUT9

OUT9Ab

OUT9A

÷R9

÷R0

÷R9A

Device

Clocks

4x SYSREF

÷N0

÷5

Figure 1.1. Si5386 Block Diagram

Si5386 Rev. E Reference Manual • Functional Description

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1.4 DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL

loop bandwidth settings in the range of 20 Hz to 4 kHz are available for selection. The DSPLL loop bandwidth register values are

determined using ClockBuilder Pro.

CBPro chooses the PLL parameters so that peaking in passband of the PLL is less than 0.1 dB.

Note: After manually changing bandwidth parameters, the BW_UPDATE bit must be set high to latch the new values into operation.

This update bit will latch the new values for Loop, Fastlock, and Holdover Exit bandwidths simultaneously.

Table 1.2. DSPLL Loop Bandwidth Registers

[Bit Field]

Function

BW_PLL 0x0508[7:0]-0x050D[7:0] Determines the loop BW for the DSPLL.

Parameters are generated by ClockBuilder

Pro.

BW_UPDATE 0x0514[0] Writing a 1 to this register bit will latch

Loop, Fastlock, and Holdover Exit BW pa-

rameter registers.

1.4.1 Fastlock

Selecting a low DSPLL loop bandwidth (e.g., 20 Hz) will generally lengthen the lock acquisition time. The Fastlock feature allows

setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process to reduce lock time. Higher Fastlock loop

bandwidth settings will enable the DSPLLs to lock faster. Fastlock Bandwidth settings up to 4 kHz are available for selection. Fastlock

bandwidth should generally be set from 10x to 100x the loop bandwidth for optimal results. Once lock acquisition has completed,

the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. The Fastlock feature can be enabled or

disabled independently by register control.

Note: The BW_UPDATE_PLLx update bit will latch new values for Loop, Fastlock, and Holdover Exit bandwidths simultaneously.

Table 1.3. DSPLL Fastlock Bandwidth Registers

[Bit Field]

Function

FASTLOCK_BW_PLL 0x050E[5:0]-0x0513[5:0] Determines the Fastlock BW for the DSPLL. Parameters

are generated by ClockBuilder Pro.

FASTLOCK_AUTO_EN 0x052B[0] Auto Fastlock Enable/Disable.

0: Disable Auto Fastlock (default)

1: Enable Auto Fastlock

FASTLOCK_MAN 0x052B[1] Force Fastlock.

0: Normal Operation (default)

1: Force Fastlock

The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL feature can be found in section 3.3 Fault Monitoring.

Si5386 Rev. E Reference Manual • Functional Description

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1.4.2 Holdover Exit Bandwidth

In additional to the Loop and Fastlock bandwidths, a user-selectable bandwidth is available when exiting holdover and locking or

relocking to an input clock when ramping is disabled (HOLD_RAMP_BYP = 1). CBPro sets this value equal to the Loop bandwidth by

default. Note that the BW_UPDATE bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.

Table 1.4. DSPLL Holdover Exit Bandwidth Registers

[Bit Field]

Function

HOLDEXIT_BW 0x059D[5:0]–0x05A2[5:0] Determines the Holdover Exit BW for

the DSPLL. Parameters are generated by

ClockBuilder Pro.

1.5 Dividers Overview

There are four divider classes within the Si5386. Figure 1.1 Si5386 Block Diagram on page 7 shows all of these dividers. All divider

values for the Si5386 may be either Fractional or Integer. For best phase noise performance, integer dividers are preferred.

• P0-P3: Input clock wide range dividers (0x0208–0x022F)

• 48-bit numerator, 32-bit denominator

•Min. value is 1; Max. value is 224 (Fractional-P divisors must be > 5)

• Practical range limited by phase detector and VCO range

• Each divider has an update bit that must be written to cause a newly written divider value to take effect.

• Soft Reset All will also update the P divider values

• M: DSPLL feedback divider (0x0515–0x051F)

• 56-bit numerator, 32-bit denominator

•Max. value is 224 (Fractional-M divisors must be > 10)

• Practical range limited by phase detector and VCO range

• The M divider has an update bit that must be written to cause a newly written divider value to take effect.

• Soft Reset will also update M divider values.

• The DSPLL includes an additional divide-by-5 in the feedback path. Manually calculated M divider register values must be

adjusted accordingly.

• N: Output divider (0x0302-0x0338)

• 44-bit numerator, 32-bit denominator

•Min. value is 5, Max. value is 224 (Fractional-N divisors must be > 10)

• Each N divider has an update bit that must be written to cause a newly written divider value to take effect.

• Soft Reset will also update N divider values.

• R: Final output divider (0x0247-0x026A)

• 24-bit field

•Min. value is 2, Max. value is 225-2

• Only even integer divide values: 2,4,6, etc.

• R Divisor=2 x (Field +1). For example, Field=3 gives an R divisor of 8.

Si5386 Rev. E Reference Manual • Functional Description

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2. Modes of Operation

After initialization, the DSPLL will operate in one of the following modes: Free run, Lock-Acquisition, Locked, VCO Freeze, or Holdover.

These modes are described further in the sections below.

No valid

input clocks

selected

Lock Acquisition

(Fast Lock)

Locked

Mode

Holdover

Mode

Phase lock on

selected input

clock is achieved

An input is

qualified and

available for

selection

No valid input

clocks available

for selection

Free Run

Valid input clock

selected

Reset and

Initialization

Power-Up

Selected input

clock fails

Yes

Holdover

History

Valid?

Other Valid

Clock Inputs

Available?

Yes

Input Clock

Switch

VCO Freeze

State

An input is

qualified and

available for

selection

Figure 2.1. Modes of Operation

Si5386 Rev. E Reference Manual • Modes of Operation

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