Sony GXB5005 Manuale utente
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Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
GXB5005
SMD Type GPS Receiver Module
Description
The GXB5005 is a 12-channel GPS (Global Positioning System) receiver module.
This small module includes all the functions required for GPS and is designed for using an active antenna.
The GXB5005 can support the various kinds of the portable applications as well as the car navigation system.
Features
General
Implementation of Sony CXD2951GA-4 single chip GPS
Small size with SMD type pads and shield case
Module size (typ.): 22.4 (W) ×23.5 (D) ×3.2 (H) [mm]
Current consumption: Acquisition (typ): 70 [mA]
Tracking (typ): 41 [mA]
Battery backup (typ): 7 [μA]
Datum: WGS-84
Communication method: Supports NMEA-0183 version 3.01
Internal 32.768kHz RTC
Internal 18.414MHz TCXO
Antenna input 50Ω
Recommended antenna element
An active antenna with 0dB and RF amplifier with NF ≤2dB, 8 to 30dB gain
Functionality
12-channel GPS receiver capable of simultaneously receiving 12 satellites
All-in-view measurement
Valid fix indication output
1PPS output
WAAS/EGNOS compatible
Supported baud rate: 4800bps/9600bps/19200bps/38400bps by HW setting
Internal power on reset circuit
Antenna sense (option)
GXB5005
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Performance
Tracking sensitivity: –152dBm (typ.)
Acquisition sensitivity: –139dBm (typ.)
Time to first fix (time until initial measurement after power-on) (typ., Open sky)
Cold start (without ephemeris and almanac): 40s
Warm start (without ephemeris with almanac): 33s
Hot start (with ephemeris and almanac): 2 to 3s
Positioning accuracy (Open air with ≥–130dBm, PDOP ≤2.0)
Stand alone (GPS unit only) 2DRMS: approx. 2m
Follow-up performance: Velocity: 500km/h or less
Acceleration: 1G or less
Absolute Maximum Ratings
Operating Conditions
Item Symbol Min. Max. Unit
Power supply voltage VDD –0.5 3.7 V
Input voltage VI–0.5 5.5 V
Output voltage VO–0.5 VDD + 0.5 V
Operating temperature Topr –40 +85 °C
Storage temperature Tstg –40 +105 °C
Item Symbol Min. Typ. Max. Unit
Power supply voltage VDD 3.1 3.4 3.7 V
Power supply voltage ripple VDD-rip 50 mVp-p
Backup battery voltage Vbat 2.6 2.8 3.0 V
Input pin voltage VIN –0.3 5.5 V
Supply current: Acquisition (25°C) ICC 70 mA
Supply current: Tracking (25°C) ICC 41 mA
Standby current Istdby 7 120 μA
Operating temperature Topr –40 +25 +85 °C
Reception frequency, L1 CA code FIN 1575.42 MHz
GXB5005
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Architecture
JTAG, GPIO, etc.
CXO
32.768kHz
Host I/O
Control signal
1 bit
LNALNA SAW
BPF
Freq.
Synthesizer
LPF
Down
Converter
1.023MHz
TCXO
CPU
18.414MHz
TCXO Multiplier/
Divider
CPU
CPU, Counter
DLL, D.MF, S/P
RTC
ARM7TDMI
Time
Counter
RAM/
ROM
1.8V
Regulator
Acquisition Block
TCXO
Computation & Control Block
CMOS Radio Block
CXD2951
Baseband Unit
RF/IF Unit
Tracking Block
GXB5005
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Pin Configuration
(Top View)
Pin Description
19. 1PPS
18. B.U.
17. VDD
16. RST
15. GND
14. GND
13. Status Out
12. RF GND
11. RF IN
10. RF GND
1. AD In0
2. AD In1
3. ANT Cont
4. BR1
5. BR0
6. RXD0
7. TXD0
8. WA1
9. WA0
23.5mm
22.4mm
TCXO
CXD2951
Regulator
RF
32kHz X'tal
LNA
Shield Case Land
Pin No. Symbol I/O Description
1 AD In0 I Antenna sense input 0
2 AD In1 I Antenna sense input 1
3 ANT Cont I/O Antenna sense enable (High active)
4 BR1 I Baud rate setting 1
5 BR0 I Baud rate setting 0
6 RXD0 I UART (CH0) reception data
7 TXD0 O UART (CH0) transmission data
8 WA1 I WAAS enable 1
9 WA0 I WAAS enable 0
10 RF GND RF GND
11 RF IN I GPS signal input
12 RF GND RF GND
13 Status Out Status output
14 GND GND
15 GND GND
16 RST I Hardware reset (Low active)
17 VDD Power supply 3.4V
18 B.U. Battery backup 2.8V
19 1PPS O 1PPS output
GXB5005
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Baud Rate Setting
WAAS Enable
*1 WAAS function is set by @WA command via UART when WA1 is Low.
Baud rate BR1 BR0
4800 Open (L) H
9600 Open (L) Open (L)
19200 H Open (L)
38400 H H
WAAS WA1 WA0
Command*1 Open (L) Don’t care
Disable H Open (L)
Enable H H
GXB5005
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Electrical Characteristics
DC Characteristics
(Ta = –40 to +85°C)
AC Characteristics
(Ta = 25°C)
*1 Using SONY evaluation software “GPS View”
Timing of Output Signal
Item Symbol Condition Min. Typ. Max. Unit Pins
Supply voltage VDD 3.1 3.4 3.7 V 17
Vbat 2.6 2.8 3.0 V 18
Supply voltage ripple VDD-rip 50 mVp-p 17, 18
Input
voltage
H level VIH 2.0 5.5 V 3, 4, 5, 6, 8,
9, 16
L level VIL –0.3 0.8 V
AD VAD 0(VDD – 0.1) V 1, 2
Output
voltage
H level VOH IOH = –8mA 2.4 V 3, 7, 19
L level VOL IOL = 2mA 0.4 V
Current consumption ICC (3.3V) Acquisition 70 mA 17
Tracking 41
Istdby Vbatt = 2.8V 7 120 μA18
Item Symbol Condition Min. Typ. Max. Unit
C/N output value CN –130dBm input,
Tracking, *1 42 dB
TCXO frequency Ftcxo Internal 18.414 MHz
Message latency Tl 1.0 s
RF gain Grf 114 dB
Noise figure NF 2 dB
Output signal rise time Ttlh Zload = 5kΩ,
20pF 25 55 ns
Output signal fall time Tthl Zload = 5kΩ,
20pF 30 60 ns
5kΩ
20pF
Pin 7
(TXD0) 90%
90%
10% 10%
Ttlh
GXB5005
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Initialization
The GXB5005 has a reset pin (Pin 16) and normally this pin should be left open. The GXB5005 can perform
the power-on reset operation only by turning on or off the power supply pin (Pin 17). In addition, when
configuring the component in order to realize the reset from the system side during operation, connect the reset
pin to the external circuit. The following setting enables the reset.
1. When turning the power on (Power-on reset)
When applying the power supply to the power supply pin (Pin 17), set the reset pin (Pin 16) Low in advance,
and set it High 100ms after power-on.
2. Initialization during operation
When performing the reset while the reset pin (Pin 16) is High, keep it Low for 100μs or more before setting
High.
VDD
VDD [V]
GND
16.RST
17.VDD
VDD/2
100ms or more
VDD
GND
VDD/2
100µs or more
VDD [V]
16.RST
17.VDD
GXB5005
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Status Out
“Status Out” signal turns over
1. Definition of internal status
Searching: Searching satellites after initialization
Tracking: Navigation message decoded at least one satellite
Positioning: Position fixing
2. “Status Out” status by each internal status
Reset: Input, pulled down internally
Initialization: Output Low
Searching: Output 1s High, 1s Low turn over
Tracking: Output 0.5s High, 0.5s Low turn over
Positioning: Output High (keeping)
3. Jitter
Turns over regular pulse width ±5% max.
|T – T1| / T ≤5%
4. Status transition
Check internal status every 0.5s, only the status changes, “Status Out” output logic turns over and keeps
specified High-Low output interval.
Only status changes to positioning, “Status Out” output turns over High caused by the previous status.
0.5s
0.5s
Tracking
L
H
1.0s
L
1.0s
Searching
H
Positioning
L
H
1234
T
H
T1
T
T1
LL
H
T: Regular pulse width (1s/0.5s)
T1: Actual pulse width
Searching Tracking Positioning
1.0s
Low
High
Status Out
Change state Change state
0.5s
GXB5005
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UART Interface
Interface: Asynchronous serial interface (UART)
Baud rate: 4800bps/9600bps/19200bps/38400bps
Start bit: 1 bit
Data bit: 8 bits
Stop bit: 1 bit
Parity bit: None
Flow control: Xon/Xoff
Data output cycle: Approximately 1 second (default)
NMEA0183 Format
The GXB5005 can output 8 different types of sentence: GPGGA, GPGLL, GPGSA, GPGSV, GPRMC, GPVTG,
GPZDA and PSGSA. If 9600bps, 19200bps or 38400bps baud rate is set for port setting, it outputs 7 types of
sentence: GPGGA, GPGSA, GPGSV, GPRMC, GPVTG, GPZDA and PSGSA as default. Moreover, if 4800bps
baud rate is set, it outputs 4 types of sentences: GPGGA, GPGSA, GPGSV and GPRMC as default.
NMEA Message Output Timing
NMEA messages are output within 1s after the 1PPS pulse.
1
0
D0 D1 D2 D3 D4 D5 D6 D7
Start bit
1 bit
Data bit
8 bits
Stop bit
1 bit
LSB MSB
t + 1 t + 2 t + 3 t + 4 t + 5 t + 6 T
1PPS
NMEA
t + 1 t + 2 t + 3 t + 4 t + 5 t + 6
GXB5005
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1PPS Output
The 1PPS output provides a timing pulse synchronized to GPS time once a valid fix is available.
The figure below shows the behavior of the 1PPS output signal after reset. For a period of 160μs after reset,
the 1PPS signal outputs the system clock. The actual 1PPS signal is activated at 500ms after reset.
CPU clock exists for 160µs after reset
1PPS signal output occurs 500ms after reset
Reset
ECLKOUT (1PPS)
Reset
ECLKOUT (1PPS)
Reset
ECLKOUT (1PPS)
500ms
160µs
145ns
(6.90MHz)
Expansion
Expansion
1+
1+
1+
Indice
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