SpinCore Technologies PulseBlaster Manuale utente
PulseBlaster
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PulseBlaster™, SpinCore, and the SpinCore Technologies, Inc. logos are trademarks of SpinCore Technologies, Inc. All other
trademarks are the property of their respective owners.
SpinCore Technologies, Inc. makes every effort to verify the correct operation of the equipment. This equipment version is not
intended for use in a system in which the failure of a SpinCore device will threaten the safety of equipment or person s).
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PulseBlaster
Table of Contents
I. Introduction .............................................................................................. 5
Product Overview ..................................................................................................... 5
Board Architecture ................................................................................................... 6
Block Diagram ..................................................................................................... 6
Key Features .............................................................................................................. 6
Output Signals ...................................................................................................... 6
Timing Characteristics .......................................................................................... 7
Instruction Set ....................................................................................................... 7
External Triggering ............................................................................................... 7
Status Read ack .................................................................................................. 7
Summary .............................................................................................................. 8
Specifications ............................................................................................................ 8
Pulse Parameters ................................................................................................. 8
Pulse Program Control Flow ................................................................................ 8
Note on Related Boards Compatible with this Manual ......................................... 8
II. Installation ............................................................................................... 9
Installing the PulseBlaster ....................................................................................... 9
Testing the PulseBlaster .......................................................................................... 9
III. Programming the PulseBlaster .......................................................... 12
The PulseBlaster Interpreter .................................................................................. 12
PulseBlaster.NET .................................................................................................... 13
LabVIEW Extensions ............................................................................................... 14
PulseBlaster MATLAB GUI ..................................................................................... 15
C/C++ Programming ................................................................................................ 16
IV. Connecting to the PulseBlaster Board .............................................. 18
Connector Information ............................................................................................ 18
General Pin Assignments ....................................................................................... 18
DB25 Bracket Connector Flag 0..15 - Pin Assignments .................................... 18
SMA Connector Clock_Out ................................................................................ 19
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PulseBlaster
SMA Connector Ext_Clk ..................................................................................... 19
SP17 and PCIe Boards Specific Pin Assignments .............................................. 2
Shrouded IDC Connector Flag0..11 - Pin Assignments ..................................... 20
Shrouded IDC Connector Flag12..23 - Pin Assignments .................................. 20
Shrouded IDC Connector Flag24..26 - Pin Assignments .................................. 21
Shrouded IDC Connector HW Trig/Reset .......................................................... 22
Clock Oscillator Header .......................................................................................... 24
Appendix I: Controlling the PulseBlaster with SpinAPI ........................ 25
Introduction .............................................................................................................. 25
Instruction Set Architecture ................................................................................... 25
Machine-Word Definition .................................................................................... 25
Breakdown of 80- it Instruction Word ................................................................ 25
About SpinAPI ......................................................................................................... 28
Using C Functions to Program the PulseBlaster ................................................. 28
Example Use of C Functions .............................................................................. 31
Appendix II: Sample C Program .............................................................. 32
Appendix III: Available Firmware Designs ............................................. 34
Related Products and Accessories ........................................................ 35
Contact Information ................................................................................. 39
Document Information Page .................................................................... 39
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PulseBlaster
I. Introduction
Product Overview
The PulseBlaster device is an intelligent pulse/word/pattern/delay generator producing up to 24
precisely timed, individually controlled digital output signals.
The intelligence of the PulseBlaster timing processor comes from an embedded
microprogrammed control core uPC). The PulseBlaster processor is able to execute instructions that
allow it to control program flow. This means that the PulseBlaster processor understands Operational
Control Codes, Op Codes, and will execute them much the same way as a general-purpose
microprocessor does. Unlike general-purpose processors, the PulseBlaster processor features a
highly optimized instruction set that has been specifically designed for timing applications. A unique
and distinguishing feature of the PulseBlaster processor is that the execution time of instructions is
user programmable. This feature makes the PulseBlaster capable of executing complex output
timing patterns at greatly varying update rates, ranging from nanoseconds to years, with a constant
setting accuracy of just one clock period e.g., a 10 ns setting accuracy at a 100 MHz clock
frequency).
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PulseBlaster
Board Architecture
Block Diagram
Figure 1 presents the general architecture of the PulseBlaster system. The major building blocks
are the SRAM memory both internal and external1 to the processor), the microcontroller uPC), the
integrated bus controller IBC), the counter, and the output buffers. The entire logic design, excluding
output buffers, is contained on a single silicon chip, making it a System-on-a-Chip design. User control
to the system is provided through the IBC over the peripheral component interconnect PCI) bus.
Figure 1: PulseBlaster board architecture. The clock oscillator signal is derived from an on-chip PLL circuit
typically using a 50 MHz on-board reference clock.
Key Features
Output Signals
The PulseBlaster PB24 models allow for 24 digital output signal lines. Sixteen output lines are
routed to a DB25 bracket-mounted connector. On the SP17 and the PCIe boards, all 24 output lines
are for routed to IDCs. The PB12 models allow for 12 digital output signal lines bits 0 to 11 as
describe in the Pin Assignments). The individually controlled digital output lines comply with the
transistor-transistor logic TTL) levels’ standard, and are capable of delivering up to ±25 mA per
bit/channel. The number of output channels and current output are dependent on the board and
firmware, so make sure to see Firmware Designs . If the load being driven is less than 132 Ohms, the
1 SP46 boards do not have external S AM.
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PCI Bus
PCI Bus
PulseBlaster
voltage will drop below the TTL limit of 3.3 V. If more current is required for lower loads, users can
boost power using the SpinCore TTL Line Driver.
Timing Characteristics
The PulseBlaster’s timing controller accepts an internal on-board) crystal oscillator up to 100
MHz. The innovative architecture of the timing controller allows the processing of either simple timed
instructions with delays of up to 232 or 4,294,967,296 clock cycles), or double-length timed
instructions up to 252 clock cycles long – nearly 2 years with a 100 MHz clock!). Regardless of the
type of instruction, the timing resolution remains constant for any delay – just one clock period e.g.,
10 ns at 100 MHz).
The core-timing controller has a minimum delay cycle of five clock periods for the PB12-100-4k
and PB24-100-4k and a minimum delay cycle of nine clock periods for PB24-100-32k and PB24-100-
64k. For a 100 MHz clock, this translates to a 50.0 ns pulse/delay/update for the PB12-100-4k and
PB24-100-4k models, and a 90.0 ns pulse/delay/update for the PB24-100-32k and PB24-100-64k
models.
Instruction Set
The PulseBlaster’s design features a set of commands for highly flexible program flow control.
The micro-programmed controller allows for programs to include branches, subroutines, and loops at
up to 8 nested levels – all this to assist the user in creating dense pulse programs that cycle through
repetitious events, especially useful in numerous multidimensional spectroscopy and imaging
applications.
External Triggering
The PulseBlaster can be triggered and/or reset externally via dedicated hardware lines. These
lines combine the convenience of triggering e.g., in cardiac gating) with the safety of the "stop/reset"
line.
Status Readback
The status of the pulse program can be read in hardware or software. The hardware status
output signals consist of five IDC connector pins labeled “Status”. The same output can be read
through software using C. See Section IV Connecting to the PulseBlaster Board, page 18) for more
detail about the hardware lines and Appendix I Controlling the PulseBlaster with SpinAPI, page 25)
for more detail about the C function pb_read_status ).
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PulseBlaster
Summary
The PulseBlaster is a versatile, high-performance, programmable pulse/pattern TTL signal
generator operating at speeds of 100 MHz or more!) and capable of generating
pulses/delays/intervals ranging from 50 ns to two years per instruction. It is connected via PCI or
PCIe port and can accommodate pulse programs with highly flexible control commands of up to 64k
i.e., 65,536) program words Model PB24-100-64k). Its high-current output logic bits are individually
controlled with a voltage of 3.3 V.
Specifications
Pulse Parameters
•Up to 24 individually controlled digital output lines TTL levels, 3.3 V logical “one”)
•Variable pulses/delays for every TTL line
•Up to 25 mA output current per TTL line depends on board and firmware, see Firmware Designs )
•50 ns shortest pulse/interval for internal memory models: PB12-100-4k and PB24-100-4k
•90 ns shortest pulse/interval for external memory models: PB24-100-32k, PB24-100-64k
•2 years longest pulse/interval at 100 MHz, with the use of the “Long Delay” instruction)
•10 ns pulse/interval resolution at 100 MHz)
•Up to 64k pulse program memory words/instructions Model PB24-100-64k)
•External triggering and reset – TTL levels
Pulse Program Control low
•Loops, nested 8 levels deep
•20 bit loop counters max. 1,048,576 repetitions)
•Subroutines, nested 8 levels deep
•Latency after trigger WAIT state) – 8 clock cycle latency 80 ns at 100 MHz), adjustable to 40
seconds in duration
•5 MHz max. re-triggering frequency at 100 MHz clock frequency)
Note on Related Boards Compatible with this Manual
Much of the programming information provided in this manual is nearly universal to SpinCore's
lines of boards. More complex boards such as the PulseBlasterESR, PulseBlaster-DDS, and
RadioProcessor lines of boards still rely on the same PulseBlaster core for TTL pulse generation.
Therefore, the basic example programs for the PulseBlaster will be able to produce the same results
on any of the more complex boards. The exception is the PulseBlaster-DDS-II board which uses a
96-Bit or 124-Bit instruction word, depending on the firmware, instead of an 80-Bit instruction word
and is currently not compatible with PulseBlaster methods of programming the board.
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PulseBlaster
II. Installation
Installing the PulseBlaster
Whenever installing or uninstalling the PulseBlaster, always have it disconnected from the
computer initially. Uninstall any previous version of SpinAPI.
1. Install the latest version of SpinAPI found at: http://www.spincore.com/support/spinapi/ .
•SpinAPI is a custom Application Programming Interface developed by SpinCore
Technologies, Inc. for use with the PulseBlaster and most of SpinCore's other products. It
can be utilized using C/C++ or graphically using the options in the next section below. The
API will also install the necessary drivers.
2. Shut down the computer, unplug the power cord, insert the PulseBlaster card into an appropriate
slot PCI for PCI boards and PCIe for PCIe boards) and fasten the PC bracket securely with a
screw.
3. Plug the power cord back in, turn on the computer and follow the installation prompts.
Testing the PulseBlaster
The simplest way to test whether the PulseBlaster has been installed properly and can be
controlled as intended is to run a simple test program. These example files can be found in the
PulseBlaster24 folder in the examples folder of the SpinAPI.
The pb24_ex1.exe program will produce a square wave, on all digital outputs, with a logical
high time of 200 ms and logical low time of 200 ms. To test the board, run pb24_ex1.exe and
observe each digital output with an oscilloscope.
If using a high input impedance oscilloscope to monitor the PulseBlaster's output, place a
resistor that matches the characteristic impedance of the transmission line in parallel with the coaxial
transmission line at the oscilloscope input. e.g., a 50 Ω resistor with a 50 Ω transmission line, see
Figures 2 and 3 below).
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PulseBlaster
Figure 4 below shows a typical pattern displayed by an oscilloscope when running pb24_ex1.exe with
the above described connections. Verifying this behavior confirms the board is installed properly.
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Figure 2: Left: BNC T-Adapter and Right: BNC 50 Ohm resistor.
Figure 4: Expected signal from a PulseBlaster output running pb24_ex1.exe.
Figure 3: BNC T-Adapter on the oscilloscope input channel with coaxial transmission line
connected on the left and BNC 50 Ohm resistor connected to the right to terminate the line.
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