ST STM32F10 Series Istruzioni per l'installazione e il funzionamento

December 2022 AN2586 Rev 8 1/29

AN2586

Application note

Getting started with STM32F10xxx hardware development

Introduction

This document is addressed to system designers who need a hardware implementation

overview of the development board features, such as power supply, clock management,

reset control, boot mode settings, and debug management.

It shows how to use the low-density value line, low-density, medium-density value line,

medium-density, high-density, XL-density and connectivity line STM32F10xxx products (the

full list is detailed in Table 1), and describes the minimum hardware resources required to

develop an application. Detailed reference design schematics are also provided, with the

description of the main components, interfaces, and modes.

Table 1. Applicable products

Type Lines

Microcontrollers

STM32F100 Value Line

STM32F101

STM32F102

STM32F103

STM32F105/107

www.st.com

Contents

2/29 AN2586 Rev 8

Contents

1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 7

2.1.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3.1 Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . . 9

2.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1.1 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 13

3.2 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.1 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 14

3.3 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

AN2586 Rev 8 3/29

Contents

5.3.3 Internal pull-up and pull-down resistors on JTAG pins . . . . . . . . . . . . . . 20

5.3.4 SWJ debug port connection with standard JTAG connector . . . . . . . . . 20

6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3 Ground and power supply (VSS, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1.4 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

List of tables

4/29 AN2586 Rev 8

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. Debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4. SWJ I/O pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 6. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 7. Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

AN2586 Rev 8 5/29

List of figures

Figure 1. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 13. Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 14. STM32F103ZE(T6) microcontroller reference schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 25

General information

6/29 AN2586 Rev 8

1 General information

This document applies to STM32F10xxx microcontrollers, based on Arm®Cortex® cores.

Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or

elsewhere.

Glossary

Low-density value line devices are STM32F100xx microcontrollers where the flash

memory density ranges between 16 and 32 Kbytes.

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the flash memory density ranges between 16 and 32 Kbytes.

Medium-density value line devices are STM32F100xx microcontrollers where the flash

memory density ranges between 64 and 128 Kbytes.

Medium-density devices are STM32F100xx, STM32F101xx, STM32F102xx and

STM32F103xx microcontrollers where the flash memory density ranges between 64 and

128 Kbytes.

High-density value line devices are STM32F100xx microcontrollers where the flash

memory density ranges between 256 and 512 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the

flash memory density ranges between 256 and 512 Kbytes.

XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the

flash memory density ranges between 768 Kbytes and 1 Mbyte.

Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

AN2586 Rev 8 7/29

Power supplies

2 Power supplies

2.1 Introduction

The device requires a 2.0 to 3.6 V operating voltage supply (VDD). An embedded regulator

is used to supply the internal 1.8 V digital power.

The real-time clock (RTC) and backup registers can be powered from the VBAT voltage

when the main VDD supply is powered off.

Figure 1. Power supply overview

Note: VDDA and VSSA must be connected, respectively, to VDD and VSS.

2.1.1 Independent A/D converter supply and reference voltage

To improve the conversion accuracy, the ADC has an independent power supply that can be

filtered separately, and shielded from noise on the PCB:

•the ADC voltage supply input is available on a separate VDDA pin

•an isolated supply ground connection is provided on the VSSA pin

When available (depending on package), VREF– must be tied to VSSA.

On 100- and 144-pin packages

To ensure a better accuracy on low-voltage inputs, the user can connect a separate external

reference voltage ADC input on VREF+. The voltage on VREF+ can range from 2.4 V to VDDA.

A/D converter

I/O Ring

BKP registers

Temp. sensor

Reset block

Standby circuitry

PLL

(Wakeup logic,

IWDG)

RTC

Voltage regulator

Core

memories'

digital

peripherals

Low voltage detector

SSA

) V

REF–

DDA

domain

domain 1.8 V domain

Backup domain

LSE crystal 32 KHz oscillator

RCC BDCR register

ai14863

(from 2.4 V up to V

DDA

) V

REF+

) V

DDA

) V

SSA

) V

BAT

Power supplies

8/29 AN2586 Rev 8

On packages with 64 pins or less

The VREF+ and VREF- pins are not available, they are internally connected to the ADC

voltage supply (VDDA) and ground (VSSA).

2.1.2 Battery backup

To retain the content of the Backup registers when VDD is turned off, the VBAT pin can be

connected to an optional standby voltage supplied by a battery or another source.

The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main

digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the power

down reset (PDR) circuitry embedded in the Reset block.

If no external battery is used in the application, it is highly recommended to connect VBAT

externally to VDD.

2.1.3 Voltage regulator

The voltage regulator is always enabled after reset. It works in three different modes,

depending on the application modes:

•in Run mode, the regulator supplies full power to the 1.8 V domain (core, memories

and digital peripherals)

•in Stop mode, the regulator supplies low power to the 1.8 V domain, preserving the

contents of the registers and SRAM

•in Standby mode, the regulator is powered off. The contents of the registers and SRAM

are lost except for those concerned with the Standby circuitry and the Backup domain.

2.2 Power supply schemes

The circuit is powered by a stabilized power supply, VDD.

•The VDD pins must be connected to VDD with external decoupling capacitors (one

100 nF ceramic capacitor for each VDD pin, plus one tantalum or ceramic capacitor

(min. 4.7 µF, typ.10 µF).

•The VBAT pin can be connected to the external battery (1.8 V < VBAT < 3.6 V). If no

external battery is used, it is recommended to connect this pin to VDD with a 100 nF

external ceramic decoupling capacitor.

•The VDDA pin must be connected to two external decoupling capacitors (100 nF

ceramic + 1 µF tantalum or ceramic).

•The VREF+ pin can be connected to the VDDA external power supply. If a separate,

external reference voltage is applied on VREF+, a 100 nF and a 1 µF capacitors must be

connected on this pin. In all cases, VREF+ must be kept between 2.4 V and VDDA.

•Additional precautions can be taken to filter analog noise:

–V

DDA can be connected to VDD through a ferrite bead.

–TheV

REF+ pin can be connected to VDDA through a resistor (typ. 47 Ω).

Caution: If the ADC is used, the VDD range is limited to 2.4 to 3.6 V (when the ADC is not used, the

VDD range is 2.0 to 3.6 V).

AN2586 Rev 8 9/29

Power supplies

Figure 2. Power supply scheme

1. Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and

1 µF) must be connected.

2. VREF+ is either connected to VDDA or to VREF.

3. N is the number of VDD and VSS inputs.

2.3 Reset and power supply supervisor

2.3.1 Power on reset (POR) / power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from

2V.

The device remains in the Reset mode as long as VDD is below a specified threshold,

VPOR/PDR, without the need for an external reset circuit. For more details concerning the

power on/power down reset threshold, refer to the electrical characteristics in the low-

density, medium-density, high-density, XL-density, and connectivity line STM32F10xxx

datasheets.

Figure 3. Power on reset/power down reset waveform

VBAT

STM32F10xxx

N × 100 nF

VDD

+ 1 × 10 µF

100 nF + 1 µF

(note 1)

Battery

VBAT VREF+

VDDA

VSSA

VREF–

VDD 1/2/3/.../N

VSS 1/2/3/.../N

VREF

VDD

ai14865b

VDD/VDDA

40 mV

hysteresis

PDR

MS30431V2

Reset

Temporization

tRSTTEMPO

VPOR/PDR

rising edge

VPOR/PDR

falling edge

Power supplies

10/29 AN2586 Rev 8

2.3.2 Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD power supply by comparing it to a threshold

selected by the PLS[2:0] bits in the Power control register (PWR_CR).

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate

whether VDD is higher or lower than the PVD threshold. This event is internally connected to

EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD

output interrupt can be generated when VDD drops below the PVD threshold and/or when

VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge

configuration. As an example the service routine can perform emergency shutdown tasks.

Figure 4. PVD thresholds

2.3.3 System reset

A system reset sets all registers to their reset values except for the reset flags in the clock

controller CSR register and the registers in the Backup domain (see Figure 1).

A system reset is generated when one of the following events occurs:

1. A low level on the NRST pin (external reset)

2. Window watchdog end-of-count condition (WWDG reset)

3. Independent watchdog end-of-count condition (IWDG reset)

4. A software reset (SW reset)

5. Low-power management reset

The reset source can be identified by checking the reset flags in the Control/Status register,

RCC_CSR.

MS30432V2

100 mV

hysteresis

PVD threshold

PVD output

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