TENX TECHNOLOGY TM59MA41 Manuale utente

Advance

Information

0tenx technology, inc.

Preliminary Rev 1.2, 2008/05/19

TM59MA41

User’s Manual

tenx technology, inc.

Advance Information UM-TM59MA41_E

1tenx technology, inc.

Preliminary Rev 1.2, 2008/05/19

Contents

Chapter 1. Overview ................................................................................... 2

1-1. Feature.................................................................................................................. 2

1-2. Clock Scheme and Instruction Cycle................................................................. 5

1-3. Addressing Mode................................................................................................. 5

1-4. ALU and Working (W) Register........................................................................... 6

1-5. STATUS Register.................................................................................................. 6

1-6. Interrupt ................................................................................................................ 7

1-7. Reset ..................................................................................................................... 7

1-8. Power-Down Mode............................................................................................... 8

1-9. System Config Register....................................................................................... 8

1-10. Instruction Set.................................................................................................... 10

Chapter 2. Control Register ..................................................................... 21

Chapter 3. Timer0,1................................................................................... 40

Chapter 4. 8-Bit PWM................................................................................ 43

Chapter 5. 12-Bit PWM.............................................................................. 45

Chapter 6. Analog to Digital Converter................................................... 47

Chapter 7. I/O Ports................................................................................... 49

Chapter 8. Buzzer Out .............................................................................. 53

Chapter 9. Flash Memory Interface ......................................................... 55

Chapter 10. Electrical Characteristics....................................................... 56

10-1. Absolute Maximum Ratings.............................................................................. 56

10-2. DC Characteristics............................................................................................. 56

10-3. Clock Timing Constants.................................................................................... 57

10-4. External Interrupt Characteristics.................................................................... 58

10-5. A/D Converter Electrical Characteristics......................................................... 58

10-6. Reset Timing Characteristics............................................................................ 59

10-7. LVR Circuit Characteristics............................................................................... 59

Chapter 11. Packaging Information........................................................... 60

11-1. 20-DIP Package Dimension ............................................................................... 61

11-2. 20-SOP Package Dimension.............................................................................. 62

11-3. 20-SSOP Package Dimension ........................................................................... 63

11-4. 16-DIP Package Dimension ............................................................................... 64

11-5. 16-SOP Package Dimension.............................................................................. 65

11-6. 16-SSOP Package Dimension ........................................................................... 66

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Preliminary Rev 1.2, 2008/05/19

Chapter 1. Overview

1-1. Feature

1. ROM: 4K x 14 bits flash memory (MTP)

2. RAM: 192 x 8 bits

3. STACK: 6 Levels

4. I/O ports: Three I/O ports (Max 18 pins) and Bit programmable ports

5. Timer/counter: Two 8-bit timer/counter (or one 16-bit) with time interval modes

6. Watchdog Timer: On chip WDT based on system oscillator

7. Power-On Reset & Watchdog timer overflow Reset & Low Voltage detector reset

8. Oscillation Frequency:

z1 MHz to 12 MHz external crystal oscillator

zInternal RC: 4.6 MHz (typ.) in VDD = 5 V

zExternal RC

9. High-speed PWM:

z8-bit PWM 1-ch, 6-bit base + 2-bit extension (Max: 156 kHz)

z12-bit PWM 1-ch, 6-bit base + 6-bit extension (Max: 156 kHz)

10. Operation Voltage:

z2.0 to 5.5V (LVR disable)

zLVR to 5.5V (LVR enable)

11. Instruction set: 35 Instructions

12. Execution Time: 167 ns at 12 MHz fOSC (minimum)

13. A/D Converter: 10-bit conversion resolution with 10-ch analog input pins (MAX)

14. Interrupts: 5 interrupt sources with one vector with one interrupt level

15. Buzzer Out: Frequency Selectable Buzzer Output

16. System Config Option:

zLVR Level Selection zLVR/IVC control in STOP mode

zn Reset pin Selection zClock Source Selection

zRead protection control

17. Reset vector: 000H

18. Interrupt vector: 001H

19. Power Down mode

20. Package Types:

z20-SOP, SSOP, DIP z16-SOP, SSOP, DIP

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Name In/Out Pin Description Shared Function

PA.0–PA.7 I/O

Bit-programmable I/O port for Schmitt-trigger input or

push-pull output. Pull-up resistors are assignable by

software. PortA pins can also be used as A/D converter

input, PWM output or external interrupt input.

ADC0-ADC7

INT0/INT1

PWM0/PWM1

PB.0–PB.1 I/O

Bit-programmable I/O port for Schmitt-trigger input or

push-pull, open-drain output. Pull-up resistors or pull-

down resistors are assignable by software.

XIN,XOUT

PB.2 I Schmitt trigger input port nRESET

nRESET I External Reset input PB.2

PC.0–PC.6 I/O

Bit-programmable I/O port for Schmitt-trigger input or

push-pull, open-drain output. Pull-up resistors are

assignable by software.

ADC8-9/CLO

T0OUT/BUZZER

XIN,XOUT – Crystal/Ceramic, or RC oscillator signal for system clock. PB.0–PB.1

VDD,VSS P Voltage input pin and ground –

CLO O System clock output port PC.6

INT0–INT1 I External interrupt input port PA.0, PA.1

PWM0 O 8-Bit high speed PWM output PA.6

PWM1 O 12-Bit high speed PWM output PA.7

T0OUT O Timer0 match output PC.0

ADC0–ADC9 I A/D converter input PA.0–PA.7

PC.5–PC.6

< Table 1-1. PIN Description > < I: Input; O: Output; I/O: Bi-direction; P: Power >

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1-2. Clock Scheme and Instruction Cycle

The clock input (XIN) is internally divided by two to generate Q1 state and Q2 state for each instruction cycle.

The Programming Counter (PC) is updated at Q1 and the instruction is fetched from program ROM and

latched into the instruction register in Q2. It is then decoded and executed during the following Q1-Q2 cycle.

Fetch Execute

Branch

Instruction

Pipeline

Flow Fetch Execute

Fetch Flush

Fetch Execute

Instruction

Cycle

FOSC

Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2

< Figure 1-5. Clock/Instruction cycle and pipeline >

Branch instructions take two cycles since the fetch instruction is ‘flushed’ from the pipeline, while the new

instruction is being fetched and then executed.

1-3. Addressing Mode

The Programming Counter is 12-bit wide capable of addressing a 4K x 14 program ROM. As a program

instruction is executed, the PC will contain the address of the next program instruction to be executed. The

PC value is normally increased by one except the followings. The Reset Vector (000h) and the Interrupt

Vector (001h) are provided for PC initialization and Interrupt. For CALL/GOTO instructions, PC loads 12 bits

address from instruction word and the MSB from STATUS’s bit 6. For RET/RETI/RETLW instructions, PC

retrieves its content from the top level STACK. For the other instructions updating PC[7:0], the PC[11:8]

keeps unchanged. The STACK is 12-bit wide and 6-level in depth. The CALL instruction and Hardware

interrupt will push STACK level in order, While the RET/RETI/RETLW instruction pops the STACK level in

order.

The data memory is partitioned into two banks, which contain the General Purpose Data Memory and the

Special Function Registers (SFR). STATUS.4 is the bank select bits. Each bank extends up to 7Fh (128

bytes). The lower locations of each bank (00h-1Fh) are reserved for the SFR. Above the SFR is General

Purpose Data Memory, implemented as static RAM. SFR area is mirrored in all banks for code reduction and

quicker access.

The first half of RAM (00h – 3Fh) is bit-addressable.

Data memory can be addressed directly or indirectly. Indirect Addressing is made by INDF register. The

INDF register is not a physical register. Addressing INDF actually addresses the register whose address is

contained in the FSR register (FSR is a pointer). Reading INDF itself indirectly (FSR=0) will produce 00h.

Writing to the INDF register indirectly results in a no-operation.

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Program Memory

0000 Reset Vector

0001 Interrupt Vector

0FFF

Program ROM Page0

< Figure 1-6. Address space >

1-4. ALU and Working (W) Register

The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. In two-operand

instructions, typically one operand is the W register, which is an 8-bit non-addressable register used for ALU

operations. The other operand is either a file register or an immediate constant. In single operand

instructions, the operand is either W register or a file register. Depending on the instruction executed, the

ALU may affect the values of Carry(C), Digit Carry(DC), and Zero(Z) Flags in the STATUS register. The C

and DC flags operate as a /Borrow and /Digit Borrow, respectively, in subtraction.

1-5. STATUS Register

This register contains the arithmetic status of ALU and the Bank select for RAM. The STATUS register can

be the destination for any instruction, as with any other register. If the STATUS register is the destination for

an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set

or cleared according to the device logic. It is recommended, therefore, that only BCF, BSF and MOVWF

instructions be used to alter the STATUS Register because these instructions do not affect those bits.

STATUS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset Value – – – 0 – 0 0 0

R/W – – – R/W – R/W R/W R/W

Bit Description

7-5 Not Used (Must be set to 0)

SRAM: SRAM Bank Selection Bit

0: Bank 0

1: Bank 1

3 Not Used (Must be set to 0)

Zero Flag (Z)

0: the result of a logic operation is not zero

1: the result of a logic operation is zero

Decimal Carry Flag or Decimal/Borrow Flag (DC)

ADD instruction SUB instruction

1 1: a carry from the low nibble bits of the result occurred

0: no carry

1: no borrow

0: a borrow from the low nibble bits

of the result occurred

Carry Flag(C) or Borrow Flag

ADD instruction SUB instruction

0 1: a carry occurred from the MSB

0: no carry

1: no borrow

0: a borrow occurred from the MSB

Data Memory

Registers, STATUS.4=0/1

Bit addressable

RAM, STATUS.4=0

Bit addressable

RAM, STATUS.4=1

Bit addressable

RAM

STATUS.4=0

RAM

STATUS.4=1

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1-6. Interrupt

The TM59MA41 has 1 level, 1 vector and 6 sources. Each interrupt source has its own enable control bit. An

interrupt event will set its individual flag. Because TM59MA41 has only 1 vector, there is not a interrupt

priority register. The interrupt priority is determined by F/W.

Interrupt Pending

Interrupt

Vector

i-Flag

Interrupt

Source

Interrupt

Enable

< Figure 1-7. Interrupt Function Diagram >

If the corresponding interrupt enable bit has been set (INTCON), it would trigger CPU to service the interrupt.

CPU accepts interrupt in the end of current executed instruction cycle. In the mean while, A “CALL 0001”

instruction is inserted to CPU, and the i-flag is set to prevent recursive interrupt nesting. The i-flag is cleared

in the instruction after the “RETI” instruction. That is, at least one instruction in main program is executed

before service the pending interrupt. The interrupt event is edge trigged. F/W must clear the interrupt event

1-7. Reset

The TM59MA41 can be RESET in four ways.

- Power-On-Reset

- Hardware Reset by nRESET pin

- Low Voltage Reset (LVR)

- Watchdog Reset

< Figure 1-8. Reset Circuit Diagram >

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The nRESET pin must be held to low level for a minimum after the power supply comes within tolerance in

order to allow time for internal CPU clock oscillation to stabilize. The minimum required oscillation

stabilization time is approximately 2.5 ms (fOSC = 10 MHz). When the CPU is operating in normal state (VDD

and nRESET at High level), if the signal at the nRESET pin is forced Low then the Reset operation starts. All

system and peripheral control registers are set to their default hardware Reset values.

The Low Voltage Reset features static reset when supply voltage is below a reference value. The three

levels of reference voltage can be configured in SYSL register. During the STOP mode. the LVR can be

disabled to decrease power consumption. Please refer 1.8 Power-Down Mode.

The Watchdog Timer is disabled after Reset. F/W can use the CLRWDT instruction to clear and enable the

Watchdog Timer. If once enabled, the Watchdog Timer overflow and generate a chip reset signal if no

CLRWDT executed in a period of 221 oscillator’s cycle (0.25 Second for 8.192MHz crystal). The Watchdog

Timer does not work in Power-down mode to provide wake-up function. It is only designed to prevent F/W

goes into endless loop.

1-8. Power-Down Mode

The Power-down mode is activated by SLEEP instruction. During the Power-down mode, the system clock

(SYS

f) oscillation stops to minimize power consumption and all the peripherals which the same oscillator is

selected as clock source are not working. Therefore, The Power down mode can be terminated by Reset or

enabled external Interrupts (External Interrupt 0, 1). When the Power down mode is released, the clock

circuit requires oscillation stabilization time also. The STOPCON register must be set to ‘10100101b’ before

enter the STOP mode. If the STOPCON is not set to ‘10100101b’, the SLEEP instruction cause system reset.

During the STOP mode, the IVR(internal Voltage Converter) and LVR can disable power consumption. If the

system released from STOP mode, the IVC and LVR and enabled again. It can be controlled by SYSL

Vlevel which is supplied current system.

Therefore, if you want to disable IVC in STOP mode, you must select the IVC level which is appropriate to

1-9. System Config Register

The System Config Register (SYSL) is the ROM option for initial condition of the MCU. The address 2000H

is virtual address which is not reachable in F/W. It can be written by MDS and system use only.

You can configure read protection, clock source selection, reset pin control , IVR/LVR control at STOP mode

and IVR/LVR reference voltage control in SYSL register. The default value of SYSL is 3FFFh. The 13th bit is

code protection selection bit. If write this bit to 0, the data of ROM will be all 3FFFh, when user read ROM.

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Hardware TICE59 DIP switch selection bit:

Code protection selection bit

0 Code protect

1 No protect

4-5 Not used

IVC Enable bit

0 Disable IVC in stop mode

1 Enable IVC in stop mode

IVC level selection bit

0 0 Vdd in 3.3V

1 0 Vdd in 4.0V

0 1 Vdd in 5.0V

SW5

1-2

1 1 Vdd in 5.5V

PB.2 selection bit

0 nRESET input

SW4 1

1 PB.2 intput

Clock source selection bit

0 0 External crystal /ceramic oscillator

1 0 External RC

SW2 1-2

1 1 Internal RC (4.6MHz in Vdd = 5.0V)

5 Not Used

LVR Enable bit

0 Disable LVR at sleep mode

1 Enable LVR at all time

LVR level selection bit

1 0 0 3.9V

1 1 0 3.0V

0 1 1 2.3V

SW1

1-3

Other Not Used

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