1553 PCI CARD User's Manual
February 2001 10 TEST SYSTEMS, Inc.
When the channel is used as an RT, the Subsystem Flag bit in the
1553 RT status word can be set by writing to SuMMIT Register 9 or by
writing to the Control Register. A 'one' in bit 4 of the Status Register
indicates the Subsystem Flag has been set from the Control Register.
Bit 6 provides Terminal Active status from the SuMMIT which
indicates that the SuMMIT is actively processing a 1553 command. Bit 7
provides Ready status from the SuMMIT which indicates that the SuMMIT
has completed initialization or BIT, and regular execution may begin.
Bit 8, Timer Resolution, indicates the frequency selected and
applied to the Timer Clock input to the SuMMIT. When Timer Resolution is
a 'zero' the Timer Clock frequency is 250 KHz yielding a timer resolution of
4 us. When Timer Resolution is a 'one' the Timer Clock frequency is
approximately 976 Hz yielding a timer resolution of 1,024 us. Note that the
internal frequency of 24 MHz yields a timer resolution of 64 us. To use the
Timer Clock frequency for a timer resolution of 4 us or 1,024 us, bit 10 of
Register 0 in the SuMMIT must be set to a 'one'.
Bit 12, SuMMIT Page Status, indicates which page of memory the
SuMMIT is set to access. A 'zero' in bit 12 indicates Page 0 and a 'one'
indicates Page 1.
When automatic page switching is enabled, bit 14, Page Switch
Enable, is set to a 'one'.
4.2.2 Description of Control Register Bits
When a 'one' is written to a bit in the Control Register, the function
of that bit is executed. When writing to the Control Register, if both the Set
and the Reset bits are 'one' for Interrupt Enable, Subsystem Flag, Timer
Resolution, SuMMIT Page and Page Switch Enable, the function is reset.
To actually set Page Switch Enable, the SuMMIT must be in the monitor
mode.
4.3 Interrupts
The SuMMIT can be configured to generate two different interrupts
during operation. The interrupts are 125 ns pulses which are latched in the
channel Status Register. The interrupts will be sent to the PCI Interface if
1553 PCI CARD User's Manual
February 2001 11 TEST SYSTEMS, Inc.
interrupts are enabled (channel status bit 2 is 'one'). The interrupt from
Channel 0 and the interrupt from Channel 1 are ORed together to generate
the Local Interrupt 1 in the PCI Interface. The interrupt from Channel 2 and
the interrupt from Channel 3 are ORed together to generate the Local
Interrupt 2 in the PCI Interface. Once the PC is interrupted, the channel
Status Register can be read to determine which interrupt caused the
interrupt. The interrupt must be reset by writing to the channel Control
Register. If interrupts are not enabled (channel status bit 2 is 'zero'), the
interrupts can be polled by reading the channel Status Register. Interrupt
Enable is set or reset by writing to the channel Control Register.
4.4 Memory Control
Since the SuMMIT can only directly address 64K of memory, the
128K words of memory is divided into two pages of 64K words each. Page
0 is the lower half of memory and Page 1 is the upper half of memory. Page
selection is controlled via the Status/Control Register. The upper 33 words
of Page 1 are used for the Status/Control Register and the 32 internal
registers in the SuMMIT and are not be used for SuMMIT operation or data.
4.5 SuMMIT Operation
The SuMMIT operation is based on the combination of the
information written into the 32 16 bit registers in the SuMMIT and the
information written to various blocks in memory. The SuMMIT can be set
up to operate as a Bus Controller (BC), Remote Terminal (RT), Bus Monitor
(BM) or Remote Terminal/Bus Monitor (RT/M). For detailed operation of the
SuMMIT refer to the SuMMIT Product Handbook from United Technologies
Microelectronics Center, Inc., 1575 Garden of the Gods Road, Colorado
Springs, CO 80907, (800)722-1575.
4.6 Monitor Operation
A 1553 channel on a 1553 PCI CARD can be configured for monitor
operation either with or without automatic page switching.
