unicore UFirebird II Guida
UC6580 Hardware Reference Design
i
Revision History
Version
Revision History
Date
R1.0
First release
Sep.,
2023
ii
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UC6580 Hardware Reference Design
iii
Foreword
This document gives the hardware reference design of the chip UC6580 from Unicore.
Target Readers
This document applies to technicians who possess the expertise on GNSS receivers.
I
Contents
1Reference Design....................................................................................1
1.1 LDO Mode.........................................................................................................................1
1.2 DC/DC Mode.....................................................................................................................2
2Attention ................................................................................................3
2.1 Power................................................................................................................................3
2.2 Reset Signal .....................................................................................................................4
2.3 RTC....................................................................................................................................4
2.4 TCXO.................................................................................................................................5
3Recommended BOM ...............................................................................6
Appendix Simplest Design to Replace UC6226..............................................8
UC6580 Hardware Reference Design
UC-06-C21 EN R1.0 Reference Design 1
1Reference Design
If you do not need the RTC and backup function, connect V_BCKP to VDD_IO.
RTC and backup function are the prerequisites of GNSS hot start. Refer to
UC6580
Datasheet
for more details.
1.1 LDO Mode
Under the LDO mode:
DCDC_IN and VDD_IO use the same power supply;
Use the internal LDO_EX to power the system;
Power the external TCXO by LDO_X;
Connect RTC Crystal externally;
Connect LNA and SAW externally;
Use the UART interfaces to communicate;
Lower cost but higher power consumption.
RF Short 50ohm Line
TCXO
VBCKP：1.7V~3 .6V
VMAIN：2.7V~3 .6V
V_DET：2.7V~3 .6V
LDO_RE TLDO_X
LDO_X
VMAIN
DCDC_O UT
VDD_ANT
LDO_C
LDO_EX
VMAIN
VMAIN
V_DE T
V_BC KP
Figure 1-1 Reference design of LDO mode
If the antenna feed supply and the chip’s main supply use the same power rail, the
ESD, surge and overvoltage from the antenna will have an effect on the main supply,
which may cause damage to the chip. Therefore, it is recommended to design an
independent power rail for the antenna feed supply to reduce the possibility of chip
damage.
2 Reference Design UC-06-C21 EN R1.0
1.2 DC/DC Mode
Under the DC/DC mode:
DCDC_IN and VDD_IO use the same power supply;
Use the internal DC/DC to power the system;
Power the external TCXO by LDO_X;
Connect RTC Crystal externally;
Connect LNA and SAW externally;
Use the UART interfaces to communicate;
Lower power consumption but higher cost due to the use of power inductor
comparing with LDO mode;
RF Short 50ohm Line
TCXO
V_COR E
LDO_X
VMAIN
DCDC_O UT
LDO_RE TLDO_X VD D_AN T
LDO_C LDO_EX
VMAIN
VMAIN
V_DE TV_BC KP
VBCKP：1.7V~3 .6V
VMAIN：2.7V~3 .6V
V_DET：2.7V~3 .6V
Figure 1-2 Reference design of DCDC mode
If the antenna feed supply and the chip’s main supply use the same power rail, the
ESD, surge and overvoltage from the antenna will have an effect on the main supply,
which may cause damage to the chip. Therefore, it is recommended to design an
independent power rail for the antenna feed supply to reduce the possibility of chip
damage.
UC6580 Hardware Reference Design
UC-06-C21 EN R1.0 Attention 3
2Attention
2.1 Power
DCDC_IN and VDD_IO use the same external power supply. For all the power supplies,
the ripple voltages must not exceed 50 mV.
The value of LDO_X must be lower than VDD_IO and the default is 1.7 V to 1.9 V.
To improve the product stability, it is recommended to control the power on and off of
UC6580 by the controlling terminal of the power supply. When an unstable factor out of
control occurs, the terminal does power on/off operations on UC6580 to make the
system recover, which ensures a continuous work of the system.
Note:
VMAIN
The VMAIN initial level when power-on should be less than 0.4 V.
The VMAIN ramp when power-on should be monotonic, without plateaus.
The voltages of undershoot and ringing should be within 5% VMAIN.
VMAIN power-on waveform: The time interval from 10% rising to 90% must be
within 100 μs ~ 10 ms.
Power-on time interval: The time interval between the power-off (VMAIN < 0.4 V) to
the next power-on must be larger than 500 ms.
VBCKP
The VBCKP initial level when power-on should be less than 0.4 V.
The VBCKP ramp when power-on should be monotonic, without plateaus.
The voltages of undershoot and ringing should be within 5% VBCKP.
VBCKP power-on waveform: The time interval from 10% rising to 90% must be
within 100 μs ~ 10 ms.
Power-on time interval: The time interval between the power-off (VBCKP< 0.4 V) to
the next power-on must be larger than 500 ms.
4 Attention UC-06-C21 EN R1.0
2.2 Reset Signal
UC6580 supports system reset. The reset signal is active low and the active time should
be no less than 5 ms.
2.3 RTC
RTC is usually driven by an on-chip 32.768 kHz oscillator, which needs to be connected
to an external 32.768 kHz crystal.
Instead of this, UC6580 supports directly inputting RTC_I with an external 32.768 kHz
digital clock signal. In this situation, make sure that the signal amplitude is less than
1.98 V, otherwise it may cause damage to the chip.
In addition to the general rules of RTC layout and routing, you should pay special
attentions to:
Have a complete reference GND under the chip and the RTC crystal.
The RTC crystal shall be placed as close to the chip as possible, and there shall be
no other devices between the two;
Devices, signals, wiring, etc. with high power or strong interference should be
avoided around RTC crystal;
It is recommended to do ground shields for the relevant circuits of RTC.
UC6580 Hardware Reference Design
UC-06-C21 EN R1.0 Attention 5
2.4 TCXO
The CLK_I pin connects an external TCXO of 26 MHz. The power supply of TCXO can be
LDO_X or an external independent LDO power supply.
In order to ensure the chip boots normally, the 26 MHz clock should work stably no later
than 10 ms after the chip is powered.
The basic parameter requirements for TCXO are as follows:
Frequency and temperature: 26 MHz ± 0.5 ppm (-40 °C to +85 °C);
Short-term frequency stability: < 5 ppb/s.
Special attentions should be paid to the layout and routing of TCXO in addition to the
general rules:
It is recommended to maintain copper void for the layer where TCXO is placed and
the adjacent layers, and keep the reference ground complete for other layers, so as
to reduce the impact of heat conduction on the performance of TCXO.
Place TCXO as close to the chip as possible, with ground shields for the
surrounding
circuits.
Avoid placing any high-power or strong interference devices, signals, traces, etc.
around the TCXO. Keep a distance of more than 3 times the trace width between the
clock signal trace and other traces.
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