Vitrek V15X-AA11 Manuale

Model V15X-AA11

Installation and Setup

The Model V15X-AA11 is shipped in an anti-static bag with a styrofoam packing container.

Carefully remove the module from its anti-static bag and prepare to set the various options to

conform to the operating environment. Make sure that all anti-static precautions are taken to

avoid damaging the module.

For an initial test the V15X-AA11 and the VME Single Board Computer (SBC) may be plugged

together without any modification needed.

The following chart shows the strap/switch selections along with their default configurations.

If any of the user requirements vary from the default configuration, consult the following

sections for changing the parameter. Please refer to Appendix A of this manual for the location

of the straps and switches on the V15X-AA11.

Selectable Parameter Default Value

Slot0/Non-Slot0 Configuration Slot 0 Configuration

Logical Address 0

System Controller Enabled

Slot0 Configuration

The V15X-AA11 may be configured as a Slot0 controller or as a non-Slot0 controller. The

V15X-AA11 is shipped from the factory as a Slot0 controller. Several strap and switch setting

must be set to enable the V15X-AA11 Slot0 functionality. Refer to the SBC manual for

enabling the System Controller.

The V15X-AA11 must first be setup as system controller to assume the responsibilities of a

Slot0 controller. A switch setting on the V15X-AA11 must be set. The switch on the V15X-

AA11 is labeled SW2 and the switch location of interest is position 1. This switch must be

placed in the OPEN (1) position to allow the V15X-AA11 to function as a Slot0 controller. This

switch controls the direction of the VXIbus signals SYSCLK and BCLR. If the V15X-AA11

adapter is configured as a system controller, the must also be configured the same way.

The next selection to be made concerns the VXIbus MODID (Module ID) signal and an internal

signal on the V15X-AA11 indicating Slot0 operation. These selections are made via three of the

switch positions of switch SW2. Position 2 controls the internal indication for Slot0 operation.

This switch must be set to the OPEN (1) position for Slot0 operation. Position 3 of switch SW2

controls the MODID signal 825 ohm pulldown resistor. When the V15X-AA11 is in a Slot0

position, this switch must be set to the OPEN (1) position to disconnect the resistor from the

MODID signal since this resistor is provided on the VXI chassis backplane for the Slot0

position.

Model V15X-AA11

Position 4 of switch SW2 controls the connection of the 16.8Kohm pullup resistor to the MODID

signal. When the V15X-AA11 is configured as a Slot0 device, this switch position must be

CLOSED (0) to allow the MODID signal to be terminated with the pull-up resistor

The remaining setup of the V15X-AA11 adapter concerns the VXIbus signal CLK10. The

CLK10 signal is a 10 Megahertz timing clock generated by the Slot0 controller. A differential

ECL driver drives this signal onto the VXIbus. A set of straps on the V15X-AA11 adapter

controls whether this signal is sourced onto VXI by the internal clock of the V15X-AA11 or not

sourced by the V15X-AA11. To alter the selection, two straps must be moved. The V15X-AA11

is configured at the factory to source the CLK10 signal from the internal clock. This is enabled

by placing the two CLK10 straps into the INTERNAL position. You need to enable this for

Slot0 operation.

This concludes the configuration of the V15X-AA11 adapter for Slot0 operation. The SBC must

also be configured to operate as a system controller. Please refer to the SBC manual for

strap/switch locations along with a description of changing operating parameters.

Non-Slot0 Configuration

To setup the V15X-AA11 as a non-Slot0 device, the module must first be disabled from being

the system controller. The system controller function is usually an operation provided by a

Slot0 controller. A switch setting on the V15X-AA11 must be set. The switch on the V15X-

AA11 is labeled SW2 and the switch location of interest is position 1. This switch must be

placed in the CLOSED (0) position to allow the V15X-AA11 to function as a non-Slot0 device.

This switch controls the direction of the VXIbus signals SYSCLK and BCLR. Setting this

switch to the CLOSED (0) position enables the V15X-AA11 to receive the SYSCLK and BCLR

signals for non-Slot0 applications. If the V15X-AA11 adapter is not configured as a system

controller, the SBC must also be configured the same way.

The next selections to be made concerns the VXIbus MODID (Module ID) signal and an

internal signal on the V15X-AA11 indicating Slot0 operation. These selections are made via

three of the switch positions of switch SW2. Position 2 controls the internal indication for Slot0

operation. This switch must be set to the CLOSED (0) position for non-Slot0 operation.

Position 3 of switch SW2 controls the MODID signal 825 ohm pulldown resistor. If the V15X-

AA11 is to operate in a non-Slot0 configuration, this switch must be set to the CLOSED (0)

position allowing the pulldown resistor to connect to the MODID signal.

Position 4 of switch SW2 controls the connection of the 16.8Kohm pull-up resistor to the

MODID signal. When the V15X-AA11 is to be used in a non-Slot0 configuration, this switch

position must be set to the OPEN (1) position to disconnect the pull-up resistor from the

MODID signal.

The remaining setup of the V15X-AA11 adapter concerns the VXIbus signal CLK10. The

CLK10 signal is a 10 Megahertz timing clock generated by the Slot0 controller. A set of straps

on the V15X-AA11 adapter controls whether this signal is sourced onto VXI by the internal

clock of the V15X-AA11 or not sourced by the V15X-AA11. To alter the selection, two straps

must be moved. The V15X-AA11 is configured at the factory to source the CLK10 signal from

the internal clock. To disable driving CLK10, place the two CLK10 straps into the NC position.

This concludes the configuration of the V15X-AA11 adapter for non-Slot0 operation. The SBC

Model V15X-AA11

must also be configured to disable the system controller portion of the SBC. Please refer to the

SBC manual for strap/switch locations along with a description of changing operating

parameters.

Logical Address

The V15X-AA11 may be configured to operate as either a Slot0 controller or a non-Slot0

controller. When the V15X-AA11 is the Slot0 controller, it must be located in the left-most slot

(Slot0) and be set for Logical Address 0. If the V15X-AA11 is not the Slot0 controller, it may be

located in any other slot in the chassis and set for Logical Address 1 through 255. To statically

assign a Logical Address to the V15X-AA11, simply set the 8-position DIP switch to the desired

Logical Address in the range of 1 through 254. This sets the Logical Address of the V15X-AA11

and may only be altered by changing the setting on the DIP switch.

The V15X-AA11 may also be Dynamically Configured. A device that is Dynamically Configured

must have its Logical Address set to 255 (FF16). A device that is Dynamically Configured has

its Logical Address set by the Resource Manager when the Logical Address Register of the

V15X-AA11 is written. Dynamic Configuration is used to avoid conflicts in setting up a devices’

Logical Addresses. The Resource Manager makes use of the feature of the VXIbus to address

the various devices set at Logical Addresses of 255. This is accomplished by using the MODID

(Module Identification) signal, which provides a geographic addressing mechanism to each

individual slot location. A normal A16 address space transfer cycle is executed to a device with

its MODID signal asserted. This differentiates one device at Logical Address 255 from another.

After the device is addressed geographically, it is written with a new Logical Address number

assigned by the Resource Manager. Dynamic Configuration eliminates the need to preassign

Logical Addresses in a VXI chassis, as long as they are all set to 255 and allocated by the

Resource Manager.

The V15X-AA11 contains a set of 8 DIP switches used to set the Logical Address. These

switches represent a binary combination of numbers in the range of 0 to 255. The switch

settings are made by depressing each Logical Address switch to the desired location. A switch

that is in the OPEN position yields a bit set to a one. A switch that is in the CLOSED position

yields a bit set to a zero. The left-most switch corresponds to Logical Address bit 128 and the

right-most switch corresponds to Logical Address bit 1. Please refer to Appendix A for the

location and setting of the Logical Address switches. The following diagram shows the bit

pattern for the A16 Logical Base Address.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

128

1000000

Bits 15 and 14 are set to one (VXI defined).

Bits 13 through 6 are user selectable using the Logical Address switches LA128 - LA1.

Bits 5 though 0 are set to 0 to indicate the beginning of a 64 byte block.

For statically configured devices, the setting of the Logical Address switches locks the devices’

Configuration Registers in A16 address space. Each device has an allocated configuration

Model V15X-AA11

address space of 64 bytes. The Logical Base Address of a device in A16 address space may then

be calculated using the following equation:

A16 Base Address = 0xC000 + (Logical Address shifted left 6 places)

For example, the A16 Base Address of a device set for Logical Address 2 is 0xC080. For a

device set to Logical Address 2, the following bit pattern is established for the base address.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1100000010000000

CLK10 Signal Generation

The VXIbus CLK10 signal is a 10 Megahertz differential ECL clock driven onto the bus by the

Slot0 controller. If the V15X-AA11 is used as a Slot0 controller, it must be configured to drive

this VXIbus signal. The signal source may be generated internally by the V15X-AA11.

A set of six straps, located near the P1/P2 connector for VXI, is used to configure the source of

the CLK10 signal. This set of straps actually controls the 2 CLK10 signals, +CLK10 and -

CLK10. When the straps are installed in the INT (INTERNAL) position, the CLK10 signals

are driven by a clock source on the V15X-AA11. If the V15X-AA11 is to be located in a non-

Slot0 position in the chassis, the CLK10 signals must be disabled from driving CLK10 by

placing the 2 sets of straps into the NC (NO CONNECTION) position.

Installation

After all the user selectable configuration parameters have been setup, the module may then be

inserted into the VXI chassis. If the V15X-AA11 is configured for Slot0 operation, insert the

V15X-AA11 into the left-most slot (Slot0) of the VXI chassis. For a non-Slot0 configuration,

insert the V15X-AA11 into any slot in the range of 1 through 13.

CAUTION: TURN OFF MAINFRAME POWER BEFORE INSERTING OR

REMOVING A VXIbus MODULE.

WARNING: REMEMBER TO REMOVE THE INTERRUPT ACKNOWLEDGE

AND BUS GRANT DAISY CHAIN JUMPERS BEFORE

INSERTING A VXI MODULE

The VXIbus backplane must be properly configured before inserting a VXI module and applying

power. The Interrupt Acknowledge jumper must be removed from the slot in which the VXI

module is to be inserted. The Bus Grant jumpers must also be removed from the slot in which

the VXI module is to be inserted. All unoccupied slot locations must have the Interrupt

Acknowledge and Bus Grant jumpers installed so that the interrupt and grant continuity is not

disrupted by any open slots. When using backplanes that auto-configure, these steps are not

Model V15X-AA11

necessary since the installation of a VXI module in the chassis makes the required

configuration occur.

VXIbus Configuration Registers and Operational Registers

The following table shows the various registers located in A16 space for the V15X-AA11 Slot 0

Controller.

A16 Offset Write Access Read Access

0016 Logical Address Register Identification

0216 Reserved Device Type Register

0416 Status/Control Register Status/Control Register

0616 Reserved Reserved

0816 Write Signal Register Protocol Register

0A16 Reserved Response Register

0C16 Reserved Reserved

0E16 Data Low Register Data Low Register

1016 Reserved Reserved

1216 Reserved Reserved

1416 Reserved Reserved

1616 Reserved Reserved

1816 Reserved Reserved

1A16 Reserved Reserved

1C16 Reserved Reserved

1E16 Reserved Reserved

2016 Reserved Suffix High Register

2216 Reserved Suffix Low Register

2416 Reserved Serial Number High Register

2616 Reserved Serial Number Low Register

2816 Module ID Register Module ID Register

2A16 Reserved Interrupt Status Register

2C16 Interrupt Control Register Interrupt Control Register

2E16 Trigger Interrupt Mask Trigger Interrupt Source

3016 Trigger Interrupt Source Clear Reserved

3216 Trigger Source Register Reserved

3416 Trigger Timer Configuration Register Reserved

3616 Reserved Reserved

3816 SBC Slave Mode Configuration Reserved

3A16 Location Monitor Interrupt Control Register Interrupt Status ID Register

3C16 Miscellaneous Control Register Read Signal Register

3E16 Reserved Version Number Register

ID/Logical Address Register

The ID/Logical Address Register is a write/read register located at an offset of 0016 from the

A16 Logical Base Address. A read operation to this register returns the Device Class, the

addressing modes of the devices’ operational registers and the Manufacturers’ Identification. A

Model V15X-AA11

write operation to this register address is typically executed by the Resource Manager during a

Dynamic Configuration allocation sequence. During the sequence, the Resource Manager

allocates a Logical Address to the V15X-AA11 by writing a logical address value to the least

significant eight bits of this register. The format and bit assignments of this register are

shown in the following diagram. Since this register has write-only and read-only bits, two bit

patterns are shown.

On read transactions: 00h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read-only 1011111100101001

Class =

Extended Addressing

Mode = A16 KineticSystems' Manufacturer ID = F2916 (3881)

Bit(s) Mnemonic Meaning

15:14 Device Class These bits are set to reflect the Device Class of the V15X-AA11.

This bit combination indicates that the V15X-AA11 is a Message

Based Device.

13:12 Address Space These bits are set to reflect the addressing mode(s) of the V15X-

AA11’s operational registers. Since all the communication

registers of the V15X-AA11 appear in A16 address space, the bits

in this field are both set to one.

11:0 Manufacturer This field reflects the manufacturer of a VXI device. This value is

3881(F2916) for KineticSystems.

On write transactions: 00h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write-only Not Used Logical Address

Bit(s) Mnemonic Meaning

15:8 Not Used These 8 bits are not used. A write operation to these bits has no effect

on the V15X-AA11.

7:0 128-LA1 Logical Address 128 through 1 are write-only bits used to set the

V15X-AA11’s Logical Address during a Dynamic Configuration cycle

executed by the Resource Manager. A Dynamic Configuration

sequence is performed on a VXI module when its logical address has

been set to 255 (FF16).

Device Type Register

The Device Type Register is a read-only register located at an offset of 0216 from the A16

Logical Base Address of the V15X-AA11. This register contains the Model Code of the V15X-

AA11. Since the V15X-AA11 is an A16-only device, the entire 16-bits of this field is used for

the Model Code.

Model V15X-AA11

Model Codes for VXI Slot0 devices must be in the range of 0016 to FF16. Model Codes for non-

Slot0 devices must be in the range of 10016 to FFFF16. When the V15X-AA11 is configured for

non-Slot0 operation, the Model Code returned in this register is 15216. When the V15X-AA11 is

configured for Slot0 operation, the 10016 bit is set to zero, yielding a Model Code of 5216.

V15X-AA11 Model Codes:

15216 for non-Slot0 configurations

5216 for Slot0 configurations

The following diagram shows the bit pattern for the Device Type Register for both Slot0 and

non-Slot0 configurations.

For Slot0 Configurations:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read-only0000000001010010

For non-Slot0 Configurations:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read-only0000000101010010

Status/Control Register

The Status/Control Register is a write/read register located at an offset of 0416 from the A16

Logical Base Address of the V15X-AA11. This register contains write-only, read-only and

write/read bits. This register is used to monitor the Module ID VXI signal, control the

assertion of SYSFAIL, control Soft Reset, and check the status of the Power-On Self Test. The

following two diagrams show the Status/Control Register, one for read accesses and one for

write.

For read operations executed to the Status/Control Register: 04h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read-Write 0MOD

ID* 1111111111RDYPASS

SYS

INH

SFT

RST

Bit(s) Mnemonic Meaning

15 Not Used This bit is not used and read as a zero.

14 MODID* This bit is set to a one if the module is not selected with the MODID

line on the VXI P2 connector. A zero indicates that the module is

selected by the MODID signal.

Model V15X-AA11

Bit(s) Mnemonic Meaning

13:4 Not Used These bits are not used and read as zeros.

3 READY Ready is a read-only bit that is set to a one indicating successful

completion of register initialization.

2 PASS Pass is a read-only bit that is set to a one when the V15X-AA11 has

completed its power-on self-test without any errors. If an error occurs,

this bit is set to a zero and the SYSFAIL signal is asserted by the

V15X-AA11.

1 SYS INH SYSFAIL INHIBIT. Reading this bit as a one indicates that the V15X-

AA11 is prevented from driving the backplane SYSFAIL line.

0 SFT RST SFT RST This bit is read as a one when the V15X-AA11 has been

placed into the Soft Reset state. Writing this register with this bit set

to a zero removes the V15X-AA11 from the soft reset state.

For write operations executed to the Status/Control Register: 04h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write-only Not Used SYS

INH

SFT

RST

Bit(s) Mnemonic Meaning

15:2 Not Used These bits are not used for write operations.

1 SYS INH SYSFAIL INHIBIT is a write/read bit used to inhibit the V15X-AA11

from asserting the backplane signal SYSFAIL. Setting this bit to a

one disables the assertion of SYSFAIL and a zero enables the signal.

0 SFT RST SOFT RESET is a write/read bit used to reset the V15X-AA11.

Setting this bit to a one places the V15X-AA11 in the soft reset state

and writing the bit to a zero removes the V15X-AA11 from the reset

state.

Protocol Register

The Protocol Register is a read-only register located at an offset of 0816 from the A16 Logical

Base Address of the V15X-AA11. The Protocol Register is accessed by executing a read to this

address location and the Signal Register is accessed by writing to this location. The Protocol

following diagram shows the bit layout of the Protocol Register of the V15X-AA11.

Model V15X-AA11

08h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read-only CMDR* SGNL

REG* MSTR*INTRFHS*11111111111

Bit(s) Mnemonic Meaning

15 CMDR* COMMANDER is a read-only bit that is set to a one for a device that

only capable of Message Based Servant functions. A zero in this bit

location indicates that the device is capable of both Commander and

Servant Message Based functions. The V15X-AA11 sets this bit to a

zero indicating it has both Commander and Servant capability.

14 SGNL-REG* SIGNAL REGISTER is a read-only bit that is set to a one for a device

that does not contain a Signal Register. Devices that contain a Signal

functional Signal Register, this bit is set to a zero

13 MSTR* MASTER is a read-only bit that is set to a one for devices that do not

have VMEbus mastering capability. A zero for this bit location

indicates the device has the ability to become a VMEbus master. The

V15X-AA11 has VMEbus mastering capability and sets this bit to a

zero.

12 INTR INTERRUPTER is a read-only bit that indicates whether the device

can generate interrupts. A zero in this bit location indicates no

interrupting ability and a one indicates that the device can generate

interrupts. The V15X-AA11 can generate interrupts and sets this bit

to a one.

11 FHS*FAST HANDSHAKE is a read-only bit used to indicate whether a Message

based devices’ data register supports the Fast Handshake Mode.

This bit is set to a one if Fast Handshake is not supported and a zero

if Fast Handshake is supported. The V15X-AA11 does not support

the Fast Handshake transfer mode and sets this bit to a one.

10 SHR MEM* SHARED MEMORY is a read-only bit used to indicate if a device

implements shared memory. A zero in this bit location indicates that

shared memory is supported and a one indicates that it is not. The

V15X-AA11 does contain some amount of shared memory, but it does

not comply with the VXI specification for Shared Memory. Therefore,

the V15X-AA11 sets this bit to a one.

9:0 Not Used These bits are not used by the V15X-AA11 and returned as ones.

Write Signal Register

The Write Signal Register is a write-only register located at an offset of 0816 from the A16

Logical Base Address of the V15X-AA11. A write operation to this register address accesses the

Model V15X-AA11

Signal Register. This register is used for device to device signaling. This register can be read

at offset 3C16 in A16 address space. A signal received from a device contains the devices’

Logical Address along with a field for device specific information. There are two different

formats for the Signal Register, depending on the value of the most significant bit (bit 15). The

following two diagrams show the various formats.

08h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write-only 0 Response Logical Address

08h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write-only 0 Event Logical Address

The fields shown for the two Signal Register patterns are as follows:

Response: This field reflects bits 14 through 8 of the device’s Response Register.

Event: This field reflects the event associated with the signal.

Logical Address: This field reflects the Logical Address of the device generating the signal.

Response Register

The Response Register is a read-only register located at an offset of 0A16 from the A16 Logical

Base Address of the V15X-AA11. This register is used to return the status of a device’s

communication registers and their associated functions. The following diagram shows the bit

layout for the Response Register on the V15X-AA11. 0Ah

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read-only 0100ERR*

READ

RDY

WRT

RDY 111111111

Bit(s) Mnemonic Meaning

15 Not Used This bit is not used and read as a zero.

14 Not Used This bit is not used and read as a one.

13:12 Not Used These two bits are not used by the V15X-AA11 and returned

as zeros.

11 ERR ERROR is a read-only bit used to signify when an error

occurs in one of the serial protocols and has not yet been

reported. This bit is set and cleared by using the

Miscellaneous Control

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