Xilinx LogiCORE IP AXI Manuale utente

LogiCORE IP AXI

Bridge for PCI Express

v2.4

Product Guide

Vivado Design Suite

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PG055 June 4, 2014

Table of Contents

IP Facts

Chapter 1: Overview

Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 2: Product Specification

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bridge Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Parameter Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Chapter 3: Designing with the Core

General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Shared Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

AXI Transactions for PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Transaction Ordering for PCIe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Malformed TLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Abnormal Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Root Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Chapter 4: Design Flow Steps

Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Chapter 5: Example Design

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Simulation Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Implementation Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Example Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Example Design Output Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Chapter 6: Test Bench

Appendix A: Migrating and Upgrading

Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Appendix B: Debugging

Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Transceiver Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Appendix C: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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Introduction

The Xilinx®LogiCORE™ IP AXI Root Port/

Endpoint (RP/EP) Bridge for PCI Express® core

is an interface between the AXI4 and PCI

Express. Definitions and references are

provided in this document for all of the

functional modules, registers, and interfaces

that are implemented in the AXI Bridge for PCI

Express core. Definitions are also provided for

the hardware implementation and software

interfaces to the AXI Bridge for PCI Express core

in supported FPGA devices.

Features

• Zynq®-7000, Kintex®-7, Virtex®-7, and

Artix®-7 FPGA Integrated Blocks for PCI

Express

• Maximum Payload Size (MPS) up to 256 bytes

• Multiple Vector Messaged Signaled Interrupts

(MSIs)

•Legacyinterruptsupport

• Memory-mapped AXI4 access to PCIe® space

• PCIe access to memory-mapped AXI4 space

• Tracks and manages Transaction Layer Packets

(TLPs) completion processing

• Detects and indicates error conditions with

interrupts

• Optimal AXI4 pipeline support for enhanced

performance

• Compliant with Advanced RISC Machine

(ARM®) Advanced Microcontroller Bus

Architecture 4 (AMBA®) AXI4 specification

• Supports up to three PCIe 32-bit or 64-bit

PCIe Base Address Registers (BARs) as

Endpoint

• Supports a single PCIe 32-bit or 64-bit BAR as

Root Port

IP Facts

LogiCORE IP Facts Table

Core Specifics

Supported

Device

Family(1)

Zynq-7000, 7 Series(1)

Supported

User Interfaces AXI4

Resources See Ta b l e 2-2

Provided with Core

Design Files VHDL and Verilog

Example

Design Verilog

Test Bench Verilog

Constraints

File XDC

Simulation

Model Not Provided

Supported

S/W Driver(2) Standalone and Linux

Tested Design Flows(3)

Design Entry Vivado® Design Suite

Vivado IP integrator

Simulation For supported simulators, see the

Xilinx Design Tools: Release Notes Guide

Synthesis Vivado Synthesis

Support

Provided by Xilinx @ www.xilinx.com/support

Notes:

1. For a complete list of supported devices, see the Vivado IP

catalog. See also Table 2-1, page 11.

2. Standalone driver details can be found in the SDK directory

(<install_directory>/doc/usenglish/xilinx_drivers.htm). Linux

OS and driver support information is available from

wiki.xilinx.com.

3. For the supported versions of the tools, see the

Xilinx Design Tools: Release Notes Guide.

4. Except for XC7VX485T, Virtex 7 devices are not supported.

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PG055 June 4, 2014

Chapter 1

Overview

The AXI Bridge for PCI Express® core is designed for the Vivado® IP integrator in the

Vivado Design Suite. The AXI Bridge for PCI Express core provides an interface between an

AXI4 customer user interface and PCI Express using the Xilinx Integrated Block for PCI

Express. The AXI Bridge for PCI Express core provides the translation level between the AXI4

embedded system to the PCI Express system. The AXI Bridge for PCI Express core translates

the AXI4 memory read or writes to PCIe Transaction Layer Packets (TLP) packets and

translates PCIe memory read and write request TLP packets to AXI4 interface commands.

The architecture of the AXI Bridge for PCI Express is shown in Figure 1-1.

X-Ref Target - Figure 1-1

Figure 1-1: High-Level AXI Bridge for PCI Express Architecture

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Chapter 1: Overview

Feature Summary

The AXI Bridge for PCI Express core is an interface between the AXI4 and PCI Express. It

contains the memory mapped AXI4 to AXI4-Stream Bridge and the AXI4-Stream Enhanced

Interface Block for PCIe. The memory-mapped AXI4 to AXI4-Stream Bridge contains a

Bridge. The Slave Bridge connects to the AXI4 Interconnect as a slave device to handle any

issued AXI4 master read or write requests. The Master Bridge connects to the AXI4

Interconnect as a master to process the PCIe generated read or write TLPs. The core uses a

set of interrupts to detect and flag error conditions.

The AXI Bridge for PCI Express core supports both Root Port and Endpoint configurations.

• When configured as an Endpoint, the AXI Bridge for PCI Express core supports up to

three 32-bit or 64-bit PCIe Base Address Registers (BARs).

• When configured as a Root Port, the core supports a single 32-bit or 64-bit PCIe BAR.

The AXI Bridge for PCI Express core is compliant with the PCI Express Base Specification v2.0

[Ref 5] and with the AMBA® AXI4 specification [Ref 4].

Unsupported Features

The following features are not supported in the AXI Bridge for PCI Express core.

• Tandem PROM and Tandem PCIe

• Advanced Error Reporting (AER)

Limitations

Reference Clock for PCIe Frequency Value

The refclk input used by the serial transceiver for PCIe must be 100 MHz, 125 MHz, and

250 MHz for 7 series and Zynq®-7000 device configurations. The C_REF_CLK_FREQ

parameter is used to set this value, as defined in Table 2-4, page 15.

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Chapter 1: Overview

Licensing and Ordering Information

This Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado

Design Suite under the terms of the Xilinx End User License.

Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx

Intellectual Property page. For information on pricing and availability of other Xilinx

LogiCORE IP modules and tools, contact your local Xilinx sales representative.

For more information, visit the AXI Bridge for PCI Express product page.

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Chapter 2

Product Specification

Figure 2-1 shows the architecture of the AXI Bridge for PCI Express® core.

The Register block contains registers used in the AXI Bridge for PCI Express core for

dynamically mapping the AXI4 memory mapped (MM) address range provided using the

AXIBAR parameters to an address for PCIe range.

The Slave Bridge provides termination of memory-mapped AXI4 transactions from an AXI

master device (such as a processor). The Slave Bridge provides a way to translate addresses

that are mapped within the AXI4 memory mapped address domain to the domain addresses

for PCIe. When a remote AXI master initiates a write transaction to the Slave Bridge, the

write address and qualifiers are captured and write data is queued in a first in first out

(FIFO). These are then converted into one or more MemWr TLPs, depending on the

X-Ref Target - Figure 2-1

Figure 2-1: AXI Bridge for PCI Express Architecture

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PG055 June 4, 2014

Chapter 2: Product Specification

configured Max Payload Size setting, which are passed to the Integrated Block for PCI

Express.

A second remote AXI master initiated write request write address and qualifiers can then be

captured and the associated write data queued, pending the completion of the previous

write TLP transfer to the core. The resulting AXI Slave Bridge write pipeline is two-deep.

When a remote AXI master initiates a read transaction to the Slave Bridge, the read address

and qualifiers are captured and a MemRd request TLP is passed to the core and a

completion timeout timer is started. Completions received through the core are correlated

with pending read requests and read data is returned to the AXI master. The Slave bridge is

capable of handling up to eight memory mapped AXI4 read requests with pending

completions.

The Master Bridge processes both PCIe MemWr and MemRd request TLPs received from the

integrated block for PCI Express and provides a means to translate addresses that are

mapped within the address for PCIe domain to the memory mapped AXI4 address domain.

Each PCIe MemWr request TLP header is used to create an address and qualifiers for the

memory mapped AXI4 bus and the associated write data is passed to the addressed

memory mapped AXI4 Slave. The Master Bridge can support up to four active PCIe MemWr

request TLPs.

Each PCIe MemRd request TLP header is used to create an address and qualifiers for the

memory-mapped AXI4 bus. Read data is collected from the addressed memory mapped

AXI4 Slave and used to generate completion TLPs which are then passed to the integrated

block for PCI Express. The Master bridge can handle up to four read requests with pending

completions for improved AXI4 pipelining performance.

The instantiated AXI4-Stream Enhanced PCIe block contains submodules including the

Requester/Completer interfaces to the AXI bridge and the Register block. The Register

block contains the status, control, interrupt registers, and the AXI4-Lite interface.

Standards

The AXI Bridge for PCIe core is compliant with the ARM® AMBA® AXI4 Protocol

Specification [Ref 4] and the PCI Express Base Specification v2.0 [Ref 5].

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Chapter 2: Product Specification

Performance

Figure 2-2 shows a configuration diagram for a target FPGA.

The target FPGA is filled with logic to drive the lookup table (LUT) and block RAM utilization

to approximately 70% and the I/O utilization to approximately 80%.

Maximum Frequencies

The maximum frequency for the AXI clock is 125 MHz for 7 series FPGAs.

Line Rate Support for PCIe Gen1/Gen2

The link speed, number of lanes supported, and support of line rate for PCIe are defined in

Table 2-1. Achieving line rate for PCIe is dependent on the device family, the AXI clock

X-Ref Target - Figure 2-2

Figure 2-2: FPGA System Configuration Diagram

AXI4-Lite

MicroBlaze

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Memory

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MDM

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(DC)

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Memory

(DP)

LEDs

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Interconnect

(AXI4)

Control

Interface

Subset

Interconnect

(AXI4-Lite)

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