Actions ATJ2135 Istruzioni operative

Actions ATJ2135 Product

Programming Guide

Latest Version: 1.1

Jan 2007

ATJ2135 PROGRAMMING GUIDE

Ver 1.1 Page 1 2007-1-29

Declaration

Circuit diagrams and other information relating to products of Actions Semiconductor

Company, Ltd. (“Actions”) are included as a means of illustrating typical applications.

Consequently, complete information sufficient for construction is not necessarily given.

Although the information has been examined and is believed to be accurate, Actions makes

no representations or warranties with respect to the accuracy or completeness of the

contents of this publication and disclaims any responsibility for inaccuracies. Information in

this document is provided solely to enable use of Actions’ products. The information

presented in this document does not form part of any quotation or contract of sale. Actions

assumes no liability whatsoever, including infringement of any patent or copyright, for sale

and use of Actions’ products, except as expressed in Actions’ Terms and Conditions of Sale

for. All sales of any Actions products are conditional on your agreement of the terms and

conditions of recently dated version of Actions’ Terms and Conditions of Sale agreement

Dated before the date of your order.

This information does not convey to the purchaser of the described semiconductor

devices any licenses under any patent rights, copyright, trademark rights, rights in trade

secrets and/or know how, or any other intellectual property rights of Actions or others,

however denominated, whether by express or implied representation, by estoppel, or

otherwise.

Information Documented here relates solely to Actions products described herein

supersedes, as of the release date of this publication, all previously published data and

specifications relating to such products provided by Actions or by any other person

purporting to distribute such information. Actions reserves the right to make changes to

specifications and product descriptions at any time without notice. Contact your Actions

sales representative to obtain the latest specifications before placing your product order.

Actions product may contain design defects or errors known as anomalies or errata which

may cause the products functions to deviate from published specifications. Anomaly or

“errata” sheets relating to currently characterized anomalies or errata are available upon

request. Designers must not rely on the absence or characteristics of any features or

instructions of Actions’ products marked “reserved” or “undefined.” Actions reserves these

for future definition and shall have no responsibility whatsoever for conflicts or

incompatibilities arising from future changes to them.

Actions’ products are not designed, intended, authorized or warranted for use in any life

support or other application where product failure could cause or contribute to personal

ATJ2135 PROGRAMMING GUIDE

Ver 1.1 Page 2 2007-1-29

injury or severe property damage. Any and all such uses without prior written approval of an

Officer of Actions and further testing and/or modification will be fully at the risk of the

customer.

Copies of this document and/or other Actions product literature, as well as the Terms

and Conditions of Sale Agreement, may be obtained by visiting Actions’ website at

http://www.actions-semi.com/ or from an authorized Actions representative. The word

“ACTIONS”, the Actions’ LOGO, whether used separately and/or in combination, and the

phase “ATJ2135”, are trademarks of Actions Semiconductor Company, Ltd., Names and

brands of other companies and their products that may from time to time descriptively

appear in this product data sheet are the trademarks of their respective holders; no

affiliation, authorization, or endorsement by such persons is claimed or implied except as

may be expressly stated therein.

ACTIONS DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT

LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND

ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

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SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS

OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON

CONTRACT; TORT; NEGLIGENCE OF ACTIONS OR OTHERS; STRICT LIABILITY; BREACH OF

WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE

FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER ACTIONS HAS BEEN ADVISED OF THE

POSSIBILITY OF SUCH DAMAGES OR NOT.

Additional Support

Additional product and company information can be obtained by visiting the Actions

website at: http://www.actions-semi.com

ATJ2135 PROGRAMMING GUIDE

Ver 1.1 Page 3 2007-1-29

Contents

Declaration......................................................................................................................1

Contents ..........................................................................................................................3

List of Figures .............................................................................................................. 11

List of Tables ................................................................................................................ 12

Revision History ........................................................................................................... 18

1Introduction........................................................................................................... 19

2Pin Description ..................................................................................................... 20

2.1 Pin Assignment ..............................................................................................................20

2.2 Pin Definition..................................................................................................................21

3Functional Block and Memory Map ................................................................... 28

3.1 Functional Block Diagram ............................................................................................ 28

3.2 Memory Map ..................................................................................................................29

4Clock Management Unit (CMU) ...........................................................................31

4.1 CMU/HOSC Description ................................................................................................31

4.2 CMU/HOSC Register List ..............................................................................................35

4.2.1 CMU_COREPLL...........................................................................................................35

4.2.2 CMU_DSPPLL .............................................................................................................36

4.2.3 CMU_AUDIOPLL .........................................................................................................36

4.2.4 CMU_BUSCLK .............................................................................................................38

4.2.5 CMU_SDRCLK.............................................................................................................39

4.2.6 CMU_NANDCLK..........................................................................................................39

4.2.7 CMU_SDCLK ...............................................................................................................40

4.2.8 CMU_UARTxCLK .........................................................................................................40

4.2.9 CMU_MHACLK ............................................................................................................41

4.2.10 CMU_DMACLK ............................................................................................................ 41

4.2.11 CMU_FMCLK ...............................................................................................................42

4.2.12 CMU_MCACLK ............................................................................................................43

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4.2.13 CMU_DEVCLKEN ........................................................................................................43

4.2.14 CMU_DEVRST .............................................................................................................45

4.3 RTC/LOSC/Watch Dog/timers Block Description ....................................................46

4.4 RTC/LOSC/Watch Dog Register List........................................................................... 47

4.4.1 RTC_CTL ......................................................................................................................48

4.4.2 RTC_DHMS..................................................................................................................49

4.4.3 RTC_YMD ....................................................................................................................50

4.4.4 RTC_DHMSALM..........................................................................................................50

4.4.5 RTC_YMDALM.............................................................................................................51

4.4.6 RTC_WDCTL................................................................................................................51

4.4.7 RTC_T0CTL..................................................................................................................52

4.4.8 RTC_T0 ........................................................................................................................53

4.4.9 RTC_T1CTL..................................................................................................................53

4.4.10 RTC_T1 ........................................................................................................................53

5Interrupt Controller............................................................................................... 55

5.1 Interrupt Controller Description...................................................................................55

5.2 Interrupt Controller Register List.................................................................................56

5.2.1 INTC_PD ......................................................................................................................56

5.2.2 INTC_MSK ...................................................................................................................57

5.2.3 INTC_CFGx ..................................................................................................................58

5.2.4 INTC_EXTCTL ..............................................................................................................59

6PMU/DC-DC Converter..........................................................................................61

6.1 Description...................................................................................................................... 61

6.2 Register List....................................................................................................................62

6.3 Register Description......................................................................................................62

6.3.1 PMU_CTL.....................................................................................................................62

6.3.2 PMU_LRADC...............................................................................................................64

6.3.3 PMU_CHG....................................................................................................................65

732-BIT RISC Core.................................................................................................. 68

7.1 Coprocessor 0 Description ...........................................................................................68

7.2 Coprocessor 0 Register List .........................................................................................68

7.2.1 IntCtl Register (CP0 Register 12, Select1) ............................................................69

7.2.2 SRSCtl Register (CP0 Register 12, Select 2).........................................................70

7.2.3 SRSMap Register (CP0 Register 12, Select 3)...................................................... 71

7.2.4 Processor Identification (CP0 Register 15, Select 0)........................................... 71

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7.2.5 EBase Register (CP0 Register 15, Select 1)..........................................................72

7.2.6 Config Register (CP0 Register 16, Select 0)..........................................................72

7.2.7 Config1 Register (CP0 Register 16, Select1) ........................................................73

7.2.8 Config2 Register (CP0 Register 16, select2)......................................................... 74

7.2.9 Config3 Register (CP0 Register 16, select3)......................................................... 74

7.3 Performance Counters Description.............................................................................75

7.4 Performance Counters Register List...........................................................................75

7.4.1 PCNT_CTL.................................................................................................................... 76

7.4.2 PCNT_PCx ...................................................................................................................77

7.5 Other Reference.............................................................................................................78

8SDRAM Interface.................................................................................................. 79

8.1 SDRAM Interface Description ......................................................................................79

8.2 SDRAM Interface Register List ....................................................................................79

8.2.1 SDR_CTL .....................................................................................................................80

8.2.2 SDR_EN.......................................................................................................................81

8.2.3 SDR_CMD ...................................................................................................................81

8.2.4 SDR_STAT ...................................................................................................................82

8.2.5 SDR_AUTORFC ...........................................................................................................83

8.2.6 SDR_MODE.................................................................................................................83

8.2.7 SDR_MOBILE..............................................................................................................84

9SRAM on Chip....................................................................................................... 85

9.1 Description......................................................................................................................85

9.2 Register List....................................................................................................................85

9.2.1 SRAMOC_CTL .............................................................................................................85

9.2.2 SRAMOC_STAT ...........................................................................................................86

10 DMA/Bus Arbiter ...............................................................................................87

10.1 Description...................................................................................................................... 87

10.2 Register List.................................................................................................................... 87

10.2.1 DMA_CTL.....................................................................................................................88

10.2.2 DMA_IRQEN................................................................................................................88

10.2.3 DMA_IRQPD ...............................................................................................................90

10.2.4 DMA_MODEx ..............................................................................................................91

10.2.5 DMA_SRCx..................................................................................................................93

10.2.6 DMA_DSTx ..................................................................................................................93

10.2.7 DMA_CNTx ..................................................................................................................94

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10.2.8 DMA_REMx .................................................................................................................94

10.2.9 DMA_CMDx.................................................................................................................94

11 24-BIT DSP Core ............................................................................................... 96

11.1 Description...................................................................................................................... 96

11.2 Register List....................................................................................................................96

11.2.1 DSP_HDR0..................................................................................................................97

11.2.2 DSP_HDR1.................................................................................................................. 97

11.2.3 DSP_HDR2.................................................................................................................. 97

11.2.4 DSP_HDR3..................................................................................................................98

11.2.5 DSP_HDR4..................................................................................................................98

11.2.6 DSP_HDR5..................................................................................................................98

11.2.7 DSP_HSR6..................................................................................................................99

11.2.8 DSP_HSR7..................................................................................................................99

11.2.9 DSP_CTL......................................................................................................................99

12 Media Hardware Accelerator (MHA)............................................................. 101

12.1 Description....................................................................................................................101

12.2 Register List and Memory Map .................................................................................102

12.2.1 MHA_CTL...................................................................................................................102

12.2.2 MHA_CFG ..................................................................................................................104

12.2.3 MHA_DCSCL01 ........................................................................................................106

12.2.4 MHA_DCSCL23 ........................................................................................................106

12.2.5 MHA_DCSCL45 ........................................................................................................106

12.2.6 MHA_DCSCL67 ........................................................................................................107

12.2.7 MHA_QSCL................................................................................................................107

13 Motion Compensation Accelerator (MCA) ................................................... 108

13.1 Description....................................................................................................................108

13.2 Register List and Memory Map .................................................................................108

13.2.1 MCA_CTL ...................................................................................................................109

14 NAND FLASH Interface ..................................................................................111

14.1 Description....................................................................................................................111

14.2 Register List..................................................................................................................111

14.2.1 NAND_CTL................................................................................................................ 112

14.2.2 NAND_STATUS..........................................................................................................114

14.2.3 NAND_FIFOTIM.........................................................................................................115

14.2.4 NAND_CLKCTL..........................................................................................................116

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14.2.5 NAND_BYTECNT.......................................................................................................116

14.2.6 NAND_ADDRLO1234..............................................................................................117

14.2.7 NAND_ADDRLO56...................................................................................................117

14.2.8 NAND_ ADDRHI1234..............................................................................................117

14.2.9 NAND_ ADDRHI56.................................................................................................. 118

14.2.10 NAND_BUF0 ........................................................................................................ 118

14.2.11 NAND_BUF1 ........................................................................................................ 118

14.2.12 NAND_CMD ..........................................................................................................119

14.2.13 NAND_ECCCTL .................................................................................................... 122

14.2.14 NAND_HAMECC0................................................................................................ 123

14.2.15 NAND_HAMECC1................................................................................................ 125

14.2.16 NAND_HAMECC2................................................................................................ 126

14.2.17 NAND_HAMCEC ...................................................................................................127

14.2.18 NAND_RSE0 .........................................................................................................127

14.2.19 NAND_RSE1 ........................................................................................................ 128

14.2.20 NAND_RSE2 ........................................................................................................ 128

14.2.21 NAND_RSE3 ........................................................................................................ 129

14.2.22 NAND_RSPS0...................................................................................................... 129

14.2.23 NAND_RSPS1.......................................................................................................130

14.2.24 NAND_RSPS2.......................................................................................................130

14.2.25 NAND_FIFODATA..................................................................................................131

14.2.26 NAND_DEBUG ......................................................................................................131

15 SD/MMC Interface..........................................................................................132

15.1 Description....................................................................................................................132

15.2 Register List..................................................................................................................132

15.2.1 SD_CTL ......................................................................................................................133

15.2.2 SD_CMDRSP.............................................................................................................133

15.2.3 SD_RW ......................................................................................................................134

15.2.4 SD_FIFOCTL ..............................................................................................................135

15.2.5 SD_CMD ....................................................................................................................136

15.2.6 SD_ARG.....................................................................................................................137

15.2.7 SD_CRC7...................................................................................................................137

15.2.8 SD_RSPBUF0 ...........................................................................................................137

15.2.9 SD_RSPBUF1 ...........................................................................................................137

15.2.10 SD_RSPBUF2 .......................................................................................................138

15.2.11 SD_RSPBUF3 .......................................................................................................138

15.2.12 SD_RSPBUF4 .......................................................................................................138

15.2.13 SD_DAT..................................................................................................................138

15.2.14 SD_CLK .................................................................................................................139

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15.2.15 SD_BYTECNT ........................................................................................................139

16 YUV2RGB Interface.........................................................................................140

16.1 Description....................................................................................................................140

16.2 Register List..................................................................................................................140

16.2.1 YUV2RGB_CTL..........................................................................................................140

16.2.2 YU2RGB_DAT............................................................................................................143

16.2.3 YUV2RGB_CLKCTL ...................................................................................................143

16.2.4 YUV2RGB_FrameCount...........................................................................................143

17 USB2.0 SIE.......................................................................................................145

17.1 General Description.....................................................................................................145

18 I2C (2) Interface.............................................................................................. 146

18.1 Description....................................................................................................................146

18.2 Register List..................................................................................................................146

18.2.1 I2Cx_CTL ...................................................................................................................147

18.2.2 I2Cx_CLKDIV.............................................................................................................148

18.2.3 I2Cx_STAT .................................................................................................................148

18.2.4 I2Cx_ADDR ...............................................................................................................150

18.2.5 I2Cx_DAT ...................................................................................................................150

19 UART Interface ................................................................................................ 152

19.1 Description....................................................................................................................152

19.2 Register List..................................................................................................................152

19.2.1 UART2_CTL ...............................................................................................................153

19.2.2 UART2_RXDAT..........................................................................................................155

19.2.3 UART2_TXDAT ..........................................................................................................155

19.2.4 UART2_STAT .............................................................................................................155

20 IR Interface...................................................................................................... 157

20.1 Description....................................................................................................................157

20.2 Register List..................................................................................................................157

20.2.1 IR_PL .........................................................................................................................158

20.2.2 IR_RBC ......................................................................................................................158

21 Key Scan ..........................................................................................................159

21.1 Description....................................................................................................................159

21.2 Register List..................................................................................................................162

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21.2.1 KEY_CTL ....................................................................................................................162

21.2.2 KEY_DAT0 .................................................................................................................163

21.2.3 KEY_DAT1 .................................................................................................................164

21.2.4 KEY_DAT2 .................................................................................................................164

21.2.5 KEY_DAT3 .................................................................................................................164

22 GPIO and Multi-function Configuration ........................................................ 165

22.1 Description....................................................................................................................165

22.1.1 GPIO/Function Pin...................................................................................................165

22.1.2 Multi-function ...........................................................................................................165

22.1.3 Pad with Built-in Resistance ..................................................................................165

22.2 Register List..................................................................................................................166

22.2.1 GPIO_AOUTEN ..........................................................................................................166

22.2.2 GPIO_AINEN .............................................................................................................166

22.2.3 GPIO_ADAT ...............................................................................................................167

22.2.4 GPIO_BOUTEN ..........................................................................................................167

22.2.5 GPIO_BINEN .............................................................................................................167

22.2.6 GPIO_BDAT ...............................................................................................................168

22.2.7 GPIO_MFCTL0 ..........................................................................................................168

22.2.8 GPIO_MFCTL1 ..........................................................................................................169

22.2.9 PAD_DRV...................................................................................................................171

23 DAC and Headphone Driver........................................................................... 173

23.1 Description....................................................................................................................173

23.2 Register List.................................................................................................................. 174

23.2.1 DAC_CTL....................................................................................................................175

23.2.2 DAC_FIFOCTL............................................................................................................176

23.2.3 DAC_DAT ...................................................................................................................178

23.2.4 DAC_Debug...............................................................................................................178

23.2.5 DAC_Analog..............................................................................................................178

24 ADC................................................................................................................... 181

24.1 Description....................................................................................................................181

24.2 Register List..................................................................................................................181

24.2.1 ADC_CTL....................................................................................................................181

24.2.2 ADC_FIFOCTL........................................................................................................... 183

24.2.3 ADC_DAT .................................................................................................................. 184

24.2.4 ADC_Analog............................................................................................................. 185

24.2.5 ADC_Debug ............................................................................................................. 186

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