Novatek NT6861 Manuale utente

NT6861

8-Bit Microcontroller for Monitor

1V2.0

Features

n40 pin DIP & 42 pin SDIP package

nOperating Voltage Range: 4.5V to 5.5V

nCMOS technology for low power consumption

nCrystal oscillator or ceramic resonator* available

n6502 8-bit CMOS CPU core

n8MHz operation of frequency

n4/8/12/16/24K bytes ROM are available

n256 bytes of RAM (which stores EDID for DDC1/2B)

nOne 8-bit pre-loadable base timer

n14 channels of 8 bit PWM outputs:

6 channel with 5V open drain and 8 channel with 12V

open drain

n2 channel A/D converters with 6-bit resolution

n24 bi-directional I/O port pins and 1 I/P pin

nHsync/Vsync signal processor

nHardware sync signals polarity & freq. evaluator

nBuilt-In I2C bus interface

nSupporting VESA DDC1/2B function

nSix-interrupt sources

- INTV (Vsync INT)

- INTE (External INT with rising edge trigger)

- INTMR (Timer INT )

-INTA (Slave Address Matched INT)

- INTD (Shift Register INT)

- INTS (SCL GO-LOW INT)

nHardware watch-dog timer function

General Description

NT6861 is a monitor component µC for auto-sync and

digital controlled applications. It contains a 6502

8-bit CPU core, 256 bytes of RAM used as working RAM

and stack area, 24K bytes of ROM maximum for

programming, 14-channel 8-bit PWM D/A converters, 2-

channel A/D converters for key detection saving I/O pins,

one 8 bit pre-loadable base timer, internal Hsync and

Vsync signals processor providing mode detection,

watch-dog timer preventing system from abnormal

operation, and an I2C bus interface.

Users can store EDID data in the 128 bytes of RAM for

DDC1/2B, so that users can save the cost of dedicated

EEPROM for EDID. Half frequency output function can

save external one-shot circuit. All of these designs create

savings in component costs.

*The frequency deviation of ceramic resonator has

+/- 6% maximum.

NT6861

Pin Configuration

[OE] DAC2

DAC1

DAC0

[DB7] P27

[VPP] RESET

GND

OSCO

OSCI

[CE] P14

[A10] P12/HALFHO

[A9] P11/AD1

[A8] P10/AD0

P20 [DB0]

P07/HSYNCO [A7]

P31/SCL [A13]

DAC4 [MODE0]

DAC3 [PGM]

HSYNCI

VSYNCI/INTV/ [A14]

NT6861

16 25

P15

[A11] P13/HALFHI

P16/INTE

DAC5 [MODE1]

DAC6 [MODE2]

DAC7

P21 [DB1]

P22 [DB2]

P06/VSYNCO [A6]

P05/DAC13 [A5]

P04/DAC12 [A4]

P03/DAC11 [A3]

P02/DAC10 [A2]

P01/DAC9 [A1]

P00/DAC8 [A0]

P30/SDA [A12][DB6] P26

[DB5] P25

[DB4] P24

[DB3] P23

* [ ]: OTP Mode

[OE] DAC2

DAC1

DAC0

[VPP] RESET

GND

OSCO

OSCI

P15

[A11] P13/HALFHI

[A9] P11/AD1

[A8] P10/AD0 P00/DAC8 [A0]P16/INTE P01/DAC9 [A1]

P02/DAC10 [A2]

P03/DAC11 [A3]

P04/DAC12 [A4]

P06/VSYNCO [A6]

P07/HSYNCO [A7]

DAC6 [MODE2]

DAC5 [MODE1]

DAC4 [MODE0]

DAC3 [PGM]

HSYNCI

VSYNCI/INTV

DAC7 [A14]

NT6861U

16 27

[CE] P14

[A10] P12/HALFHO

[DB7] P27

[DB6]P26

[DB5] P25

[DB4] P24

[DB3] P23

P05/DAC13 [A5]

P31/SCL [A13]

P30/SDA [A12]

P20 [DB0]

P21 [DB1]

P22 [DB2]

* [ ]: OTP Mode

Block Diagram

Timing Generator

CPU core

6502

Interrupt

Controller

H/V Sync Signals

Processor

SRAM + STACK

256 Bytes

Watch Dog Timer

PWM DACs

I/O Ports

OSCI

OSCO

VDD

GND

HSYNCI

INTE

SCL

SDA

DAC0 - DAC7

P00 - P07

P10 - P15

P20 - P27

VSYNCO

A/D Converter AD0 - AD1

8 Bit Base Timer

P30 - P31

IIC BUS

P16

HSYNCO

HALFHI

HALFHO

DAC8 - DAC13

VSYNCI/INTV

Program ROM

4/8/12/16/24K Bytes

NT6861

Pin Descriptions

Pin No.

40 Pin 42 Pin Designation Reset Init. I/O Description

1 1 DAC2 OOpen drain 12V, D/A converter output 2

22DAC1 OOpen drain 12V, D/A converter output 1

3 3 DAC0 OOpen drain 12V, D/A converter output 0

4 4 RESET ISchmitt trigger input pin, low active reset*

5 5 VDD PPower

6 7 GND PGround

7 8 OSCO OCrystal OSC output

8 9 OSCI ICrystal OSC input

9 10 P15 I/O Bi-directional I/O pin

10 11 P14 I/O Bi- directional I/O pin

11 12 P13/HALFHI P13 I/O Bi- directional I/O pin, shared with half hsync input

12 13 P12/HALFHO P12 I/O Bi- directional I/O pin, shared with half hsync output

13 14 P11/AD1 P11 I/O Bi- directional I/O pin, shared with A/D converter channel

1 input

14 15 P10/AD0 P10 I/O Bi- directional I/O pin, shared with A/D converter channel 0

input

15 16 P16/INTE P16 ISchmitt trigger input pin with internal pull high,sharedwith

external Rising-edge trigger interrupt

16 - 23 17 - 24 P27 - P20 I/O Bi- directional I/O pin, push-pull structure with high current

drive/sink capability

*This RESET pin must be pulled high by external pulled-up resistor (5KΩsuggestion), or it will stay low

voltage to reset system all the time.

NT6861

Pin Descriptions (continued)

Pin NO.

40 Pin 42 Pin Designation Reset Init. I/O Description

24 25 P30/SDA P30 I/O Open drain 5V Bi-direction I/O pin P30, shared with SDA pin of

I2C bus schmitt trigger buffer

25 26 P31/SCL P31 I/O Open drain 5V Bi-direction I/O pin P31, shared with SCL pin of

I2C

bus schmitt trigger buffer

26 27 P00/DAC8 P00 I/O Bi-directional I/Opin,sharedwithopen drain5VD/Aconverter

output 8

27 28 P01/DAC9 P01 I/O Bi-directional I/Opin,sharedwithopen drain5VD/Aconverter

output 9

28 29 P02/DAC10 P02 I/O Bi-directional I/Opin,sharedwithopen drain5VD/Aconverter

output 10

29 30 P03/DAC11 P03 I/O Bi-directional I/Opin,sharedwithopen drain5VD/Aconverter

output 11

30 31 P04/DAC12 P04 I/O Bi-directional I/Opin,sharedwithopen drain5VD/Aconverter

output 12

31 32 P05/DAC13 P05 I/O Bi-directional I/Opin,sharedwithopen drain5VD/Aconverter

output 13

32 33 P06/VSYNCO P06 I/O Bi- directional I/O pin, shared with vsync out

33 34 P07/HSYNCO P07 I/O Bi-directional I/O pin, shared with hsync out

34 35 DAC7 OOpen drain 12V, D/A converter output

35 36 DAC6 OOpen drain 12V, D/A converter output

36 38 DAC5 OOpen drain 12V, D/A converter output

37 39 DAC4 OOpen drain 12V, D/A converter output

38 40 DAC3 OOpen drain 12V, D/A converter output

39 41 HSYNCI IDebouncing & Schmitt trigger input pin for video horizontal

sync signal, internal pull high, shared with composite sync

input

40 42 VSYNCI/INTV VSYNCI IDebouncing & Schmitt trigger input pin for video vertical sync

signal, intermally pull high, shared with external interrupt

source

-6NC

-37 NC

NT6861

Functional Descriptions

1. 6502 CPU

The 6502isan8-bit CPUthatprovides56 instructions,decimalandbinary arithmetic,thirteenaddressingmodes, trueindexing

capability, programmable stack pointer with variable length stack, a wide selection of addressable memory, and interrupt input

options.

The CPU clock cycle is 4MHz (8MHz system clock divided by 2). Refer to 6502 data sheet for more details.

Accumulator A

Index Register Y

Index Register X

7 0

Stack Pointer SP

NStatus Register P

Carry

Zero

IRQ Disable

Decimal Mode

BRK Command

Overflow

Negative

Program Counter PCH

815

7 0

PCL

1 = TRUE

1 = Result ZERO

1 = DISABLE

1 = TRUE

1 = NEG

1 = TRUE

1 = BRK

V B DIZC

Figure 1. 6502 CPU Registers and Status Flags

NT6861

2. Instruction set list

Instruction Code Meaning Operation

ADC Add with carry A + M + C→A, C

AND Logical AND A •M →A

ASL Shift left one bit C ←M7 •••M0 ←0

BCC Branch if carry clears Branch on C = 0

BCS Branch if carry sets Branch on C = 1

BEQ Branch if equal to zero Branch on Z = 1

BIT Bit test A •M, M7 →N, M6 →V

BMI Branch if minus Branch on N = 1

BNE Branch if not equal to zero Branch on Z = 0

BPL Branch if plus Branch on N = 0

BRK Break Forced Interrupt PC+2↓PC↓

BVC Branch if overflow clears Branch on V = 0

BVS Branch if overflow sets Branch on V = 1

CLC Clear carry 0 →C

CLD Clear decimal mode 0 →D

CLI Clear interrupt disable bit 0 →I

CLV Clear overflow 0 →V

CMP Compare accumulator to memory A −M

CPX Compare with index register X X −M

CPY Compare with index register Y Y −M

DEC Decrement memory by one M −1→M

DEX Decrement index X by one X −1→X

DEY Decrement index Y by one Y −1→Y

EOR Logical exclusive-OR A ⊕M →A

INC Increment memory by one M + 1→M

INX Increment index X by one X + 1→X

INY Increment index Y by one Y + 1→Y

NT6861

Instruction set list (continued)

Instruction Code Meaning Operation

JMP Jump to new location (PC+1) →PCL, (PC+2) →PCH

JSR Jump to subroutine PC + 2↓, (P+1) →PCL, (PC+2) →PCH

LDA Load accumulator with memory M →A

LDX Load Index register X with memory M →X

LDY Load Index register Y with memory M →Y

LSR Shift right one bit 0 →M7•••M0 →C

NOP No operation No operation (2 cycles)

ORA Logical OR A + M →A

PHA Push accumulator on stack A ↓

PHP Push status register on stack P ↓

PLA Pull accumulator from stack A ↑

PLP Pullstatusregisterfromstack P ↑

ROL Rotate left through carry C ←M7•••M0 ←C

ROR Rotate right through carry C →M7•••M0 →C

RTI Return from interrupt P ↑, PC ↑

RTS Return from subroutine PC ↑, PC+1→PC

SBC Subtract with borrow A −M −C→A, C

SEC Set carry 1 →C

SED Setdecimalmode 1 →D

SEI Set interrupt disable status 1 →I

STA Store accumulator in memory A →M

STX Store index register X in memory X →M

STY Store index register Y in memory Y →M

TAX Transfer accumulator to index X A →X

TAY Transfer accumulator to index Y A →Y

TSX Transfer stack pointer to index X S →X

TXA Transfer index X to accumulator X →A

TXS Transfer index X to stack Pointer X →S

TYA Transfer index Y to accumulator Y →A

* Refer to 6502 programming data book for more details.

NT6861

3. RAM: 256 X 8 bits

256 X 8-bit SRAM is used for data memory and stack. The RAM addressing range is from $0080 to $017F. From $0100 to

$017F is used as the EDID data buffer when activating DDC1/2B mode transmission. The contents of RAM are undetermined

at power-up and are not affected by system reset. Software programmers can allocate stack area in the RAM by setting stack

pointerregisterS.Becausethe 6502 default stack pointer is$01FF,programmersmustsetregister S to FFH when startingthe

program, so the stack area will map $01FF - $0180 to $00FF - $0080.

as; LDX #$FF

TXS

RAM

Unused

$0000

$0080

$0100

$00FF

$A000

$FFFF

stack pointer

$FFFE

$FFFD

$FFFC RST-L

RST-H

IRQ-L

IRQ-H

RESET vector

IRQ vector

$017F

EDID

$0180

(4/8/12/16/24K Bytes)

ROM

$0025

System Registers

Unused

$BFFF

NT6861

4. System Registers

Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

$0000 PT0 FFH P07 P06 P05 P04 P03 P02 P01 P00 RW

$0001 PT1 7FH -P16 P15 P14 P13 P12 P11 P10 RW

$0002 PT2DIR FFH P27OE P26OE P25OE P24OE P23OE P22OE P21OE P20OE W

$0003 PT2 FFH P27 P26 P25 P24 P23 P22 P21 P20 RW

$0004 PT3 03H - - - - - - P31 P30 RW

$0005 MD CON 07H -

INSEN

HSEL

S/C

MD1/ 2

$0006 HV CON 2FH HCNTOV VCNTOV HSYNCI VSYNCI HPOLI VPOLI

HPOLO

VPOLO

$0007 HCNT L 00H HCL7 HCL6 HCL5 HCL4 HCL3 HCL2 HCL1 HCL0 R

$0008 HCNT H 00H - - - - HCH3 HCH2 HCH1 HCH0 R

$0009 VCNT L 00H VCL7 VCL6 VCL5 VCL4 VCL3 VCL2 VCL1 VCL0 R

$000A VCNT H 00H - - - - VCH3 VCH2 VCH1 VCH0 R

$000B SYNCON FFH NOHALF ENHALF -FRUN FRFREQ HALFPOL ENH ENV W

$000C ENDAC FFH ENAD1 ENAD0 ENDK13 ENDK12 ENDK11 ENDK10 ENDK9 ENDK8 W

$000D AD0 REG C0

HCEND CSTA AD05 AD04 AD03 AD02 AD01 AD00 R

$000E AD1 REG 00H - - AD15 AD14 AD13 AD12 AD11 AD10 R

$000F IEX 00H - - IEINTS IEINTD IEINTA IEINTR IEINTE IEINTV W

NT6861

System Registers (continued)

Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

$0010 IRQX 00H - - IRQINTS IRQINTD IRQINTA IRQINTR IRQINTE IRQINTV R

$0011 CLR FLG 00H CLRHOV CLRVOV CLRINTS CLRINTD CLRINTA CLRINTR CLRINTE CLRINTV W

$0012 CLR WDT -0 1 0 1 0 1 0 1 W

$0013 II ADR FFH AR7 AR6 AR5 AR4 AR3 AR2 AR1 -W

$0014 II DAT 00H SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RW

$0015 II STS 08H - - START

START STOP

STOP

ENDDC TRX RXAK -R

$0016 BT 00H BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0 W

$0017 BT CON 03H - - - - - - TBS ENBT W

$0018 DACH0 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$0019 DACH1 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$001A DACH2 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$001B DACH3 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$001C DACH4 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$001D DACH5 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$001E DACH6 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$001F DACH7 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$0020 DACH8 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$0021 DACH9 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$0022 DACH10 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$0023 DACH11 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$0024 DACH12 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$0025 DACH13 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

Note:The line above a writable signal name indicate an active lowsignal

The dash line in these control register indicate an undefined bit

The address of control register from $0026 to $007F are not used.

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