NT6862-5xxxx
8-Bit Microcontroller for Monitor
1V2.2
Features
nOperating voltage range: 4.5V to 5.5V
nCMOS technology for low power consumption
n6502 8-bit CMOS CPU core
n8 MHz operation frequency
n32K/24K/16K bytes of ROM
n512 bytes of RAM
nOne 8-bit base timer
n13 channels of 8-bit PWM outputs with 5V open drain
n4 channel A/D converters with 6-bit resolution
n25 bi-directional I/O port pins (8 dedicated I/O pins)
nHsync/Vsync signals processor for separate &
composite signals which includes hardware sync
signals polarity detection and frequency counters with
2 sets of Hsync counting intervals
nHsync/Vsync polarity controlled output, 5 selectable
free run output signals and self-test patterns, auto-
mute function, half freq. I/O function
nAdd a jitter filter at the front end of Hsync input path,
reduce the jitter interference of Hysync input
nTwo built-in I
2C bus interfaces support VESA
DDC1/2B+
nTwo layers of interrupt management
NMI interrupt sources
- INTE0 (External INT with selectable edge trigger)
- INTMUTE (Auto Mute Activated)
IRQ interrupt sources
- INTS0/1 (SCL Go-low INT)
- INTA0/1 (Slave Address Matched INT)
- INTTX0/1 (Shift Register INT)
- INTRX0/1 (Shift Register INT)
- INTNAK0/1 (No Acknowledge)
- INTSTOP0/1 (Stop Condition Occurred INT)
- INTE1 (External INT with Selectable Edge Trigger)
- INTV (VSYNC INT)
- INTMR (Base Timer INT)
- INTADC (AD Conversion Done INT)
nHardware Watch-dog timer function
n40-pin P-DIP and 42-pin S-DIP packages
General Description
The NT6862 is a new generation monitor µC for auto-sync
and digital control applications. Particularly, this chip
supports various and efficient functions to allow users to
easily develop USB monitors. It contains the 6502 8-bit
CPU core, 512 bytes of RAM used as working RAM and
stack area, 32K bytes of OTP ROM, 13-channels of 8-bit
PWM D/A converters, 4-channel A/D converters for key
detection which save I/O pins, one 8-bit pre-loadable base
timer, internal Hsync and Vsync signals processor, a
Watch-dog timer which prevents the system from abnormal
operation, and two I2C bus interfaces. The user can store
EDID data in the 128 bytes of RAM for DDC1/2B, so that
user can reduce a dedicated EEPROM for EDID. A Half
frequency output function can save external one-shot
circuit. These designs are committed to reduce component
cost. The 42 pin S-DIP IC provides two additional I/O pins –
port40 & port41, Part number NT6862U represents the S-
DIP IC. For future reference, port40 & port42 are only
available for the 42 pin S-DIP IC.
